CS4341_05 CIRRUS [Cirrus Logic], CS4341_05 Datasheet
CS4341_05
Related parts for CS4341_05
CS4341_05 Summary of contents
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Stereo DAC with Volume Control Features ! 101 dB Dynamic Range ! -91 dB THD +5.0 V Power Supply ! Low Clock-Jitter Sensitivity ! Filtered Line-Level Outputs ! On-Chip Digital De-Emphasis for 32, ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4 SPECIFIED OPERATING CONDITIONS .............................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 ANALOG CHARACTERISTICS (CS4341-KS/CZZ)............................................................................... 5 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 10 SWITCHING CHARACTERISTICS ...
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SOIC ..............................................................................................................................................32 8.2 TSSOP ..........................................................................................................................................33 9. PACKAGE THERMAL RESISTANCE .................................................................................................33 10. REFERENCES ....................................................................................................................................34 11. REVISION HISTORY ..........................................................................................................................34 LIST OF FIGURES Figure 1. Output Test Load .........................................................................................................................6 Figure 2. Maximum Loading ........................................................................................................................6 Figure 3. Single-Speed Stopband Rejection ...............................................................................................8 Figure 4. ...
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CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at T SPECIFIED OPERATING CONDITIONS Parameters DC Power Supply Specified Operating Temperature (Power Applied) ABSOLUTE MAXIMUM ...
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ANALOG CHARACTERISTICS (CS4341-KS/CZZ) test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth kHz; test load (see Figure 1).) Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit ...
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ANALOG CHARACTERISTICS (CS4341-KS/CZZ) Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full-Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance Notes: 2. One-half LSB ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE tics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Parameter ...
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Figure 3. Single-Speed Stopband Rejection Figure 5. Single-Speed Transition Band (Detail) Figure 7. Double-Speed Stopband Rejection 8 Figure 4. Single-Speed Transition Band Figure 6. Single-Speed Passband Ripple Figure 8. Double-Speed Transition Band CS4341 DS298F5 ...
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Figure 9. Double-Speed Transition Band (Detail) DS298F5 Figure 10. Double-Speed Passband Ripple CS4341 9 ...
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SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Frequency SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup ...
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SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK Parameters MCLK Frequency MCLK Duty Cycle Input Sample Rate Double-Speed Mode LRCK Duty Cycle SCLK Period SCLK rising to LRCK edge SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time ...
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SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C Parameter I²C Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time ...
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SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time ...
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DC ELECTRICAL CHARACTERISTICS Parameters Normal Operation (Note 13) Power Supply Current Power Dissipation Power-down Mode (Note 14) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 15) V Nominal Voltage Q Output Impedance Maximum allowable ...
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PIN DESCRIPTION Pin Name # Pin Description RST 1 Reset (Input) - Powers down device and resets registers to their default settings. SDATA 2 Serial Audio Data (Input) - Input for two’s complement serial audio data. SCLK 3 Serial ...
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TYPICAL CONNECTION DIAGRAM 2 SDATA Serial Audio 3 SCLK Data Processor CLK External Clock 6 SCL/CCLK 7 SDA/CDIN Micro-Controlled 8 Configuration AD0/CS 1 RST 16 + 0.1 µF 1 µ 3.3 µF ...
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APPLICATIONS 4.1 Sample Rate Range/Operational Mode The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported. ...
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Input 2 MCLK/LRCK Ratio (Format 1) 512, 256, 128 384, 192 (Format 0) 512, 256, 128 4.2.2 External Serial Clock Mode The device will enter the External Serial Clock Mode whenever 16 low to ...
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De-Emphasis The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the 32, 44 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for F The frequency response of the de-emphasis curve will ...
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Power-Down To prevent transients at power-down, the device must first enter its power-down state by enabling RST or setting the PDN bit. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. ...
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Rise Time for Control Port Clock When excess capacitive loading is present on the I²C clock line, pin 6 (SCL/CCLK) may not have sufficient hysteresis to meet the standard I²C rise time specification. This prevents the use of com- ...
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tart 4.9.3a I²C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 6. 1) Initiate a START condition to the I²C bus ...
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SD A 001000 AD0 W ACK tart 4.9.4 SPI Mode In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 24 for the clock ...
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REGISTER QUICK REFERENCE Addr Function 7 0h MCLK Control Reserved Reserved Reserved Reserved Reserved Reserved MCLKDIV Reserved 0 DEFAULT 1h Mode Control 2 AMUTE 1 DEFAULT 2h Transition and Mixing Control 0 DEFAULT 3h Channel A ...
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REGISTER DESCRIPTION NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated. 6.1 MCLK CONTROL (ADDRESS 00H Reserved Reserved Reserved 0 0 6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV) Default = 0 0 ...
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DIGITAL INTERFACE FORMAT (DIF) Default = 000 - Format 0 (I² 24-bit data, Function: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are ...
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TRANSITION AND MIXING CONTROL (ADDRESS 02H SZC1 SZC0 0 1 6.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME ( Default = Disabled 1 - Enabled Function: The AOUTA and ...
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ATAPI CHANNEL MIXING AND MUTING (ATAPI) Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo) Function: The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 6 and Figure 25 ...
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Left Channel Audio Data Right Channel Audio Data 6.4 CHANNEL A VOLUME CONTROL (ADDRESS 03H) Same as CHANNEL B Volume Control. 6.5 CHANNEL B VOLUME CONTROL (ADDRESS 04H MUTEx VOLx6 VOLx5 0 0 6.5.1 MUTE (MUTE) BIT 7 ...
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VOLUME (VOLx) BIT 0-6 Default = 0 dB (No Attenuation) Function: The digital volume control allows the user to attenuate the signal increments from 0 to -90 dB. Volume settings are decoded as shown in Table ...
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PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically kHz), including distortion components. ...
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PACKAGE DIMENSIONS 8.1 SOIC 16L SOIC (150 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE e DIM MIN A 0.053 A1 0.004 b 0.013 C 0.0075 D 0.386 E 0.150 e 0.040 H 0.228 L 0.016 ∝ 0° 32 ...
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TSSOP 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.03346 b 0.00748 D 0.193 E 0.248 E1 0.169 e -- 0.026 BSC L 0.020 ∝ ...
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CDB4341 Evaluation Board Datasheet 11.REVISION HISTORY Revision F4 Added lead-free packaging information F5 Corrected Dimension e in TSSOP Package Drawing value for NOM Millimeters from 0.065 to 0.65 Contacting Cirrus Logic Support For all product questions and inquiries, contact ...