CS4341_05 CIRRUS [Cirrus Logic], CS4341_05 Datasheet - Page 12
![no-image](/images/no-image-200.jpg)
CS4341_05
Manufacturer Part Number
CS4341_05
Description
24-Bit, 96 kHz Stereo DAC with Volume Control
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS4341_05.pdf
(34 pages)
- Current page: 12 of 34
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SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C
Notes: 8. Data must be held for sufficient time to bridge the transition time, t
12
I²C Mode
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL
Fall Time of SCL
Rise Time SDA
Fall Time of SDA
Setup Time for Stop Condition
9. See “Rise Time for Control Port Clock” on page 21 for a recommended circuit to meet rise time
RST
SDA
SCL
specification.
Stop
t irs
t buf
Parameter
Start
t hdst
t
low
Figure 14. Control Port Timing - I²C Mode
t
hdd
t high
(Note 8)
(Note 9)
t sud
Symbol
Repeated
t sust
t
t
t
t
t
t
t
t
susp
f
hdst
high
Start
t
sust
hdd
sud
t
low
t
t
t
buf
scl
irs
rc
rd
fd
fc
t
hdst
t r
fc
, of SCL.
Min
500
250
4.7
4.0
4.7
4.0
4.7
4.7
0
-
-
-
-
-
t f
®
)
Stop
t susp
Max
100
300
25
25
1
-
-
-
-
-
-
-
-
-
CS4341
DS298F5
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
µs
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