CS4341_05 CIRRUS [Cirrus Logic], CS4341_05 Datasheet - Page 25

• Manufacturer Part Number: CS4341_05
• Description: 24-Bit, 96 kHz Stereo DAC with Volume Control
• Manufacturer: CIRRUS [Cirrus Logic]

6. REGISTER DESCRIPTION
NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated.
6.1
6.2
DS298F5
Reserved
AMUTE
6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV)
6.2.1 AUTO-MUTE (AMUTE)
7
0
7
1
MCLK CONTROL (ADDRESS 00H)
MODE CONTROL (ADDRESS 01H)
Function:
Function:
Default = 0
0 - Disabled
1 - Enabled
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
Default = 1
0 - Disabled
1 - Enabled
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting
is done independently for each channel. The quiescent voltage on the output will be retained and the
Mute Control pin will go active during the mute period. The muting function is affected, similar to vol-
ume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address
02h) register.
Reserved
DIF2
6
0
6
0
Reserved
DIF1
5
0
5
0
BIT 7
BIT 1
Reserved
DIF0
4
0
4
0
Reserved
DEM1
3
0
3
0
Reserved
DEM0
2
0
2
0
MCLKDIV
POR
1
0
1
1
CS4341
Reserved
PDN
0
0
0
1
25