CS4341_05 CIRRUS [Cirrus Logic], CS4341_05 Datasheet - Page 13
CS4341_05
Manufacturer Part Number
CS4341_05
Description
24-Bit, 96 kHz Stereo DAC with Volume Control
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS4341_05.pdf
(34 pages)
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SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™)
Notes: 10. t
DS298F5
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
spi
only needed before first falling edge of CS after RST rising edge. t
sclk
< 1 MHz.
CCLK
CDIN
RST
CS
Parameter
t srs
t spi
Figure 15. Control Port Timing - SPI Mode
t r2
t css
t scl
t f2
t dsu t
(Note 10)
(Note 12)
(Note 12)
(Note 11)
t sch
dh
Symbol
f
t
t
t
t
t
t
t
t
sclk
dsu
csh
css
sch
t
t
srs
spi
scl
dh
r2
f2
---------------- -
MCLK
---------------- -
MCLK
Min
500
500
1.0
20
40
15
1
1
-
-
-
spi
t csh
= 0 at all other times.
Max
100
100
6
-
-
-
-
-
-
-
-
CS4341
MHz
Unit
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
13
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