CS4610 CIRRUS [Cirrus Logic], CS4610 Datasheet - Page 11
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CS4610
Manufacturer Part Number
CS4610
Description
CrystalClear SoundFusion PCI Audio Accelerator
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS4610.pdf
(29 pages)
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DS241PP5
Stream Processor DSP Core
The CS4610/11 Stream Processor (SP) is a custom
DSP core design optimized for processing and syn-
thesizing digital audio data streams. The SP fea-
tures a Somewhat Long Instruction Multiple Data
(SLIMD) modified dual Harvard architecture. The
device uses a 40-bit instruction word and operates
on 32-bit data words. The SP core is conservatively
rated at 300 Million Instructions per second (300
MIPS) when running at a 100 MHz internal clock
speed (CS4611 runs at 85 MHz). The SP includes
two Multiply-Accumulate (MAC) blocks and one
16-bit Arithmetic and Logic Unit (ALU). The
MAC units perform 20-bit by 16-bit multiplies and
have 40-bit accumulators, providing higher quality
than typical 16-bit DSP architectures.
PLL and Clock Control
The CS4610/11 includes a programmable Phase
Locked Loop (PLL) circuit which generates the
high frequency internal SP clock from a lower fre-
quency input clock. The PLL input may come from
the CS4610/11 crystal oscillator circuit or the serial
port clock (ASCLK/SCLK). The CS4610/11 Clock
Control circuitry allows gating of clocks to various
internal functional blocks to conserve power during
power conservation modes, as well as during nor-
mal modes of operation when no tasks are being
executed.
Host Interface
The CS4610/11 host interface is comprised of two
separate interface blocks which are memory
mapped into host address space. The CS4610/11
interface blocks can be located anywhere in the
host 32-bit physical address space. The interface
block locations are defined by the addresses pro-
grammed into the two Base Address Registers in
the CS4610/11 PCI Configuration Space. These
base addresses are normally set up by the system’s
Plug and Play BIOS. The first interface block (lo-
CS4610/11
CrystalClear™ SoundFusion™ PCI Audio Accelerator
cated using Base Address 0) is a 4 kByte register
block containing general purpose configuration,
control, and status registers for the device. The sec-
ond interface block (located using Base Address 1)
is a 1 MByte block which maps all of the
CS4610/11 internal RAM memories (SP Program
RAM, Parameter RAM, and Sample RAM), along
with the SP debug registers, into host memory
space. This allows the host to directly peek and
poke RAM locations on the device. The relation-
ship between the Base Address Registers in the
CS4610/11 PCI Configuration Space and the host
memory map is depicted in Figure 8.
CS4610/11 PCI Interface
The CS4610/11 provides a bus mastering PCI bus
interface which complies with the PCI Local Bus
Specification version 2.1.
PCI Bus Transactions
As a target of a PCI bus transaction, the
CS4610/11 supports the Memory Read (from
internal registers or memory), Memory Write (to
internal registers or memory), Configuration Read
(from
Configuration Write (to CS4610/11 configuration
registers), Memory Read Multiple (aliased to
Memory Read), Memory Read Line (aliased to
Memory Read), and the Memory Write and
Invalidate (aliased to Memory Write) transfer
cycles. The I/O Read, I/O Write, Interrupt
Acknowledge, Special Cycles, and Dual Address
Cycle transactions are not supported.
As Bus Master, the CS4610/11 generates the Mem-
ory Read Multiple and Memory Write transactions.
The Memory Read, Configuration Read, Configu-
ration Write, Memory Read Line, Memory Write
and Invalidate, I/O Read, I/O Write, Interrupt Ac-
knowledge, Special Cycles, and Dual Address Cy-
cle transactions are not generated.
CS4610/11
configuration
registers),
11