CS47014-CVZR CIRRUS [Cirrus Logic], CS47014-CVZR Datasheet - Page 14
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CS47014-CVZR
Manufacturer Part Number
CS47014-CVZR
Description
High Definition Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS47014-CVZR.pdf
(34 pages)
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode
14
SCP_CLK frequency
SCP_CS# falling to SCP_CLK rising
SCP_CLK low time
SCP_CLK high time
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
SCP_CLK low to SCP_CS# falling
SCP_CLK low to SCP_CS# rising
Bus free time between active SCP_CS#
SCP_CLK falling to SCP_MOSI output high-Z
1. The specification f
2. See
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested
actual maximum speed of the communication port may be limited by the firmware application.
parameter.
Section
SCP_CS#
SCP_MOSI
SCP_MISO
SCP_BSY#
SCP_IRQ#
SCP_CLK
5.8.
Parameter
1, 2
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the
f
Figure 3. Serial Control Port - SPI Slave Mode Timing
spisck
t
spicss
3
A6
t
spidsu
0
A5
1
t
spidh
Copyright 2009 Cirrus Logic
2
t
spickh
t
Symbol
spickl
f
t
t
t
t
t
t
t
t
t
t
spickh
spidov
spidsu
spicsh
spicsx
spisck
spicss
spickl
spidh
spicsl
spidz
A0
6
t
spidov
R/W
7
Min
18
18
11
5
7
-
-
-
-
-
MSB
MSB
0
(SCP_CLK PERIOD)/2
(SCP_CLK PERIOD)/2
5
t
11*DCLKP +
11*DCLKP +
spiirqh
3*DCLKP
6
Typical
LSB
LSB
7
t
spibsyl
t
spicsh
t
spicsdz
t
spiirql
F
Max
xtal
11
20
-
-
-
-
-
-
-
-
/2
DS752PP8
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns