CS47014-CVZR CIRRUS [Cirrus Logic], CS47014-CVZR Datasheet - Page 17

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CS47014-CVZR

Manufacturer Part Number
CS47014-CVZR
Description
High Definition Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
5.14 Switching Characteristics — Parallel Control Port - Intel
DS752PP8
Address setup before PCP_CS# and PCP_RD# low or PCP_CS#
and PCP_WR# low
Address hold time after PCP_CS# and PCP_RD# low or PCP_CS#
and PCP_WR# high
Read
Delay between PCP_RD# then PCP_CS# low or PCP_CS# then
PCP_RD# low
Data valid after PCP_CS# and PCP_RD# low
PCP_CS# and PCP_RD# low for read
Data hold time after PCP_CS# or PCP_RD# high
Data high-Z after PCP_CS# or PCP_RD# high
PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for
next read
PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for
next write
PCP_RD# rising to PCP_IRQ# rising
Write
Delay between PCP_WR# then PCP_CS# low or PCP_CS# then
PCP_WR# low
Data setup before PCP_CS# or PCP_WR# high
PCP_CS# and PCP_WR# low for write
Data hold after PCP_CS# or PCP_WR# high
PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for
next read
PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for
next write
PCP_WR# rising to PCP_BSY# falling
SCP_CLK
SCP_SDA
1
1
1
1
t
iicstscl
t
iicckcmd
t
iicsu
Parameter
A6
0
t
Figure 6. Serial Control Port - I
iich
1
t
iicckh
t
iicckl
A0
6
Copyright 2009 Cirrus Logic
t
iicr
R/W
7
t
iicdov
ACK
8
t
iicf
2
C Master Mode Timing
Symbol
MSB
t
t
irdirqhl
iwrbsyl
t
t
t
t
t
t
t
t
t
t
irdtw
iwpw
iwtrd
t
0
t
icdw
idhw
t
t
irpw
t
idsu
icdr
idhr
iwd
idis
iah
idd
ias
ird
32-bit High Definition Audio Decoder DSP Family
1
Min
f
iicck
24
30
30
24
30
30
5
5
0
8
0
8
8
-
-
-
-
®
Slave Mode
6
2*DCLKP + 20
Typical
LSB
7
ACK
8
CS4970x4 Data Sheet
Max
t
iicstp
18
18
12
t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
iicckcmd
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
iicbft
17

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