cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 189

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

CX25840/1/2/3 Data Sheet
102284B
8/3/05
IR TX Carrier Duty Cycle
[7:4]
[3:0]
IR Status
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
Bits
RZ
RW
RW
RO
RO
RO
R0
RO
RO
Type
Type
0000
0000
0
0
0
0
0
0
0
Default
Default
RESERVED
TSR
RSR
TBY
RBY
ROR
RTO
RESERVED
CDC
Name
Name
Conexant
Transmit FIFO Service Request
0 = If TIC=0 in IR_CNTL_REG, transmit FIFO is more than half full. If
TIC=1, transmitter is busy.
1 = IF TIC=0, transmit FIFO is half full or less.
If TIC=1, transmitter is idle. Generate an irq request if the TSE mask bit
is set in the IR_IRQEN_REG.
Receive FIFO Service Request
0 = If RIC=0 in IR_CNTL_REG, receive FIFO is less than half full. If
RIC=1, receive FIFO is empty.
1 = IF RIC=0, receive FIFO is half full or more. If RIC=1, receive FIFO is
not empty.
Generate an IRQ request if the RSE mask bit is set in the
IR_IRQEN_REG.
Transmitter Busy (noninterruptible)
0 = Transmitter is idle
1 = Transmitter is busy
Receiver Busy (noninterruptible)
0 = Receiver is idle
1 = Receiver is busy
Receive FIFO Overrun
0 = Receive FIFO contains one or more empty entries or is full but has
not experienced an overrun.
1 = Receive FIFO has experienced an overrun, generate an irq request if
the ROE mask bit is set in the IR_IRQEN_REG.
Note(s): When an overrun occurs, data within the FIFO remains intact,
and any new data from the RX pulse width counter is lost until the FIFO
once again contains one or more empty entries.
Receive Pulse Width Timer Time-out
0 = Receive pulse width counter has not reached its limit
1 = Receive pulse width counter has reached its limit (contains all 1s),
generate an IRQ request if the RTE mask bit is set in the IR_IRQ.
Note(s): Cleared by disabling RXE (Rx enable) bit of the
IR_CNTRL_REG
Transmit Carrier Duty Cycle
0000 = 1 TX clock high and 15 TX clocks low
0001 = 2 TX clocks high and 14 TX clocks low
0010 = 3 TX clocks high and 13 TX clocks low
...
1101 = 14 TX clocks high and 2 TX clocks low
1110 = 15 TX clocks high and 1 TX clock low
1111 = 16 TX clocks high and 0 TX clocks low
Description
Description
Address 0x20C
Address 0x210
Register Map
5-47