cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 96

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cx25840

Manufacturer Part Number
cx25840
Description
Video Decoder And Broadcast Audio
Manufacturer
Conexant Systems, Inc.
Datasheet

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Part Number
Manufacturer
Quantity
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Part Number:
cx25840-24ZP
Manufacturer:
CONEXAN
Quantity:
20 000
Detailed Functional Description
3.12
3.12.1
3.12.2
3-70
VIP 2 Host Interface
Address Space
VIP Power-Up Detection
Table 3-31. VIP Address Spaces
Address Space
The VIP 2 Host Interface provides a faster alternative interface to the two-wire serial
communication interface. The VESA VIP 2 Host slave interface is a high-bandwidth,
minimal-pin-count interface for connecting multiple video components. Refer to the
Video Electronics Standards Association (VESA) Video Interface Port, version 2
specification for full implementation details. The VIP 2 Host slave interface enables
the chip to communicate with devices that are compliant with either the VIP 1.1 or 2
master specifications. The host interface provides read accesses to the FIFO and
Read/Write accesses to the register space.
The VIP Host Interface also supports the following:
The VIP Host interface works on the VIPCLK pin, which doubles as CHIP_SEL/
VIPCLK in the two-wire serial mode. The VIP 2 Host interface block takes care of the
serialization of the data flow from the device to the a VIP Master (graphics chip) and
the serial to parallel conversion of the data flow from the VIP Master to the device.
The VIP Host interface block follows the VIP 2 specification, which stipulates that,
for reliable operation, all register accesses must be at most one wait phase per byte
and no wait phases for FIFO operations.
The VIP Master can address 4096 locations. VIP address spaces are defined in
Table
On power-up, the VIP master asserts VRST. The device holds the HAD[0] line low
until VRST remains asserted. Once the VRST is deasserted, the host interface drives
the HAD[0] line to a three-state, indicating the signal’s presence on the VIP bus.
000–00F
010–FFF
Burst reads of the registers with at most one wait phase per byte
Power management configuration through writes into the command register
Power reporting in the status registers
3-31.
VIP configuration space
Local register space
Conexant
Block
Select bit
Reg_sel
Vip_sel
CX25840/1/2/3 Data Sheet
102284B
8/3/05

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