cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 21

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

CX25840/1/2/3 Data Sheet
Table 2-1. Pin Descriptions (3 of 4)
102284B
8/3/05
VID_DATA[7:0]
HRESET/PRGM2
FIELD/PRGM1
DVALID/PRGM0
IR_TX/PRGM6
IR_RX/PRGM5
SER_CLK/HAD[0]
SER_DATA/HAD[1]
CHIP_SEL/VIPCLK/
VIPCLK
VRESET/HCTL/
PRGM3
PIXCLK
Pin Name
Pin Name
Pin Name
24 25,
26, 27,
32, 33,
34, 35
21
22
23
8
9
16
15
17
18
36
Pin
Pin
Pin
O
I/O
I/O
I/O
O
I
I/O
I/O
I
I/O
O
Dir
Dir
Dir
D
D
D
D
D, R
D
Od
Od
D
D, R
D
Type
Type
Type
Eight most significant bits of rounded video data. Data is output in a YCrCb 4:2:2
format. For 10-bit mode, the fractional, least significant two bits can be programmed
to be output on any of the PRGMx pins
Horizontal reset timing indication is the default pin function. Alternatively, the pin can
be programmed to function as a different video timing control; least significant video
data bits or GPIO. See
programmable alternative functions.
Field indication is the default pin function. Alternatively, the pin can be programmed
to function as a different video timing control; least significant video data bits or
GPIO. See
alternative functions.
Data valid indication is the default pin function. Alternatively, the pin can be
programmed to function as a different video timing control; least significant video
data bits or GPIO. See
programmable alternative functions.
Infrared remote control transmit output. Can also be configured for GPIO and video
timing control if infrared control is not needed. Also acts as a pin strap option during
reset. If the pin is low during the deassertion of RESET_N the device will boot-up in
VIP host port communications mode. If the pin is high during the deassertion of
RESET_N the device will boot-up in two-wire serial communications mode.
Infrared remote control receive input. Can also be configured for GPIO and video
timing control if infrared control is not needed.
Serial communications clock or VIP host address/data bit 0. Used for accessing
internal registers.
Serial communications data or VIP host address/data bit 1. Used for accessing
internal registers.
Serial communications mode chip select. Selects 7-bit serial chip address:
0: 1000100 (0x88 write, 0x89 read)
1: 1000101 (0x8A write, 0x8B read)
VIP host port clock in VIP host mode.
Can also be configured for GPIO and video timing control if interrupt not needed. In
VIP Host port mode, this also acts as the VIRQ_N signal. Also acts as a pin strap
option during reset. If the IRQ_N pin is low during the deassertion of RESET_N the
device will respond to the alternate two-wire serial communications address:
0x8C/0x8D when CHIP_SEL/VIPCLK/VIPCLK pin is low
0x8E/0x8F when CHIP_SEL/VIPCLK/VIPCLK pin is high
If the pin is high during the deassertion of RESET_N the device will respond to the
default two-wire serial communications addresses:
0x88/x89 when CHIP_SEL/VIPCLK/VIPCLK pin is low
0x8A/0x8B when CHIP_SEL/VIPCLK/VIPCLK pin is high
In VIP host port mode acts as control pin that is used to begin, end, or throttle data
transfers. VIP host port available only on CX25837. When the device is in serial
communications mode the pin acts as VRESET or can be configured for alternate
pin functions.
Pixel clock. Operates at 27.0 MHz and for square pixel formats, 29.5 MHz (625-line)
and 24.545 MHz (525-line).
Table 2-2
Description: {4} Control interface: Serial or VIP Host Port
Conexant
and
Description: {12} Video Output Signals
Table 2-2
Table 2-2
Figures 2-1
Description: {2} Infrared
and
and
Figures 2-1
and
Figures 2-1
2-2
for the available programmable
and
and
2-2
2-2
for the available
for the available
Pin Descriptions
2-3