C509-L_97 SIEMENS [Siemens Semiconductor Group], C509-L_97 Datasheet - Page 62

• Manufacturer Part Number: C509-L_97
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.4
The XRAM in the C509-L is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
4.4.1 XRAM Access Control
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM. XMAP0 is a
general access enable/disable control bit and XMAP1 controls the external signal generation during
XRAM accesses.
Special Function Register SYSCON (Address B1 H )
Bit
–
XMAP1
XMAP0
When bit XMAP1 in SFR SYSCON is set, during all accesses to the XRAM RD and WR become
active and port 0 and 2 drive the actual address/data information which is read/written from/to the
XRAM. This feature allows to check externally the internal data transfers to the XRAM. When port 0
and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the
port 0 and port 2 lines is interrupted.
Semiconductor Group
B1 H
XRAM Operation
Bit No. MSB
CLKP PMOD
The functions of the shaded bits are not described in this section.
7
Function
Reserved bits for future use.
XRAM visible access control
Control bit for RD/WR signals during XRAM accesses. If addresses are
outside the XRAM address range or if XRAM is disabled, this bit has no
effect.
XMAP1 = 0: The signals RD and WR are not activated during accesses to
XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during
Global XRAM access enable/disable control
XMAP0 = 0: The access to XRAM is enabled.
XMAP0 = 1: The access to XRAM is disabled (default after reset!).
6
5
1
the XRAM
accesses to XRAM. In this mode, address and data
information during XRAM/CAN Controller accesses are
visible externally.
All MOVX accesses are performed via the external bus.
Further, this bit is hardware protected.
RMAP
4
4-10
3
–
2
–
XMAP1
1
External Bus Interface
Reset Value : 1010XX01 B
XMAP0
LSB
0
SYSCON
1997-10-01
C509-L