RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 12

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.4
3.5
3.6
3.7
Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the RM5261A
implements a 5-stage integer pipeline. In addition to the integer pipeline, the RM5261A
implements an extended 7-stage pipeline for floating-point operations.
The RM5261A multiplies the input
pipeline clock.
Figure 3 shows the RM5261A integer pipeline. As illustrated in the figure, up to five integer
instructions can be executing simultaneously.
Figure 3 Pipeline
Register File
The RM5261A has thirty-two general purpose registers with register location 0 (r0) hard-wired to
a zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
ALU
The RM5261A ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in a single processor cycle.
Integer Multiply/Divide
The RM5261A has a dedicated integer multiply/divide unit optimized for high-speed multiply and
multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on
each operation.
1A-2A:
2A-2D:
I1
I2
I3
I4
I0
1I-1R:
2W:
2R:
1D:
1A:
1A:
2A:
2I:
1I
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Data cache access and load align
Register file write
Store Align
Data virtual to physical address translation
2I
1R
1I
2R
2I
1A
1R
1I
2A
2R
2I
SysClock
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
1D
1A
1R
1I
2D
2A
2R
2I
by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the
1W
1D
1A
1R
one cycle
1I
2W
2D
2A
2R
2I
1W
1D
1A
1R
2W
2D
2A
2R
1W
1D
1A
2W
2D
2A
1W
1D
2W
2D
Preliminary
1W
2W
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