RM5261A-300-HI PMC [PMC-Sierra, Inc], RM5261A-300-HI Datasheet - Page 26

• Manufacturer Part Number: RM5261A-300-HI
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when VccOK is asserted. Bit 255 is the last bit transferred.
Table 4 Boot-Time Mode Bit Stream
Mode
bit
0
4:1
7:5
8
10:9
11
12
14:13
Description
reserved (must be zero)
Write-back data rate
Pclock to SysClock Multiplier
Specifies byte ordering. Logically ORed with
BigEndian input signal.
Non-Block Write Protocol
Timer Interrupt Enable/Disable
Reserved: Must be zero
Output driver strength - 100% = fastest
Mode Bits 7:5
0: DDDD
1: DDxDDx
2: DDxxDDxx
3: DxDxDxDx
4: DDxxxDDxxx
5: DDxxxxDDxxxx
6: DxxDxxDxxDxx
7: DDxxxxxxDDxxxxxx
8: DxxxDxxxDxxxDxxx
9-15 reserved
0: Little endian
1: Big endian
00: R4000 compatible
01: reserved
10: pipelined
11: write re-issue
0: Enable the timer interrupt on Int5*
1: Disable the timer interrupt on Int5*
00: 67% strength
01: 50% strength
10: 100% strength
11: 83% strength
000
001
010
011
100
101
110
111
Multiply by 8
Multiply by 2
Multiply by 3
Multiply by 4
Multiply by 6
Multiply by 9
Multiply by 5
Multiply by 7
Mode Bit 20=0
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Multiply by 4.5
Multiply by 2.5
Multiply by 3.5
n/a
n/a
n/a
n/a
n/a
Mode Bit 20=1
Mode
bit
15
17:16
19:18
20
21
22
255:23 Reserved: Must be zero
Description
Reserved: Must be zero
System configuration identifiers -
software visible in Config[21..20]
register
Reserved: Must be zero
Select Pclock to SysClock Multiply
Mode
External Bus Width
VccIO Setting
0: Integer Multipliers
1: Half-Integer Multipliers
0: 64-bit
1: 32-bit
0: VccIO = 3.3V
1: VccIO = 2.5V
Preliminary
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