SC16IS750IPW NXP [NXP Semiconductors], SC16IS750IPW Datasheet
SC16IS750IPW
Available stocks
Related parts for SC16IS750IPW
SC16IS750IPW Summary of contents
Page 1
SC16IS740/750/760 Single UART with I and receive FIFOs, IrDA SIR built-in support Rev. 06 — 13 May 2008 1. General description The SC16IS740/750/760 is a slave I performance UART. It offers data rates Mbit/s and guarantees low ...
Page 2
NXP Semiconductors eight programmable I/O pins (SC16IS750 and SC16IS760 only) I RS-485 driver direction control via RTS signal I RS-485 driver direction control inversion I Built-in IrDA encoder and decoder interface I SC16IS750 supports IrDA SIR with ...
Page 3
... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name SC16IS740IPW TSSOP16 SC16IS750IBS HVQFN24 SC16IS750IPW TSSOP24 SC16IS760IBS HVQFN24 SC16IS760IPW TSSOP24 SC16IS740_750_760_6 Product data sheet Single UART with I Description plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; ...
Page 4
NXP Semiconductors 5. Block diagram Fig 1. Fig 2. SC16IS740_750_760_6 Product data sheet Single UART with I SC16IS750/760 RESET SCL SDA C-BUS A1 IRQ 1 k (3.3 V) 1 I2C/SPI ...
Page 5
NXP Semiconductors Fig 3. Fig 4. SC16IS740_750_760_6 Product data sheet Single UART with I SC16IS750/760 RESET SCLK CS SO SPI SI IRQ 1 k (3.3 V) 1 I2C/SPI XTAL1 XTAL2 Block diagram of SC16IS750/760 SPI ...
Page 6
... IRQ 7 10 RTS 8 9 SPI V 002aab974 1 24 RTS 2 23 GPIO7/ GPIO6/ GPIO5/DTR 5 20 GPIO4/DSR SC16IS750IPW 7 18 GPIO3 SC16IS760IPW 8 17 GPIO2 9 16 GPIO1 GPIO0 11 14 IRQ 002aab399 © NXP B.V. 2008. All rights reserved ...
Page 7
NXP Semiconductors terminal 1 index area 1 RESET XTAL1 2 XTAL2 3 SC16IS750IBS SC16IS760IBS I2C Transparent top view C-bus interface Fig 7. Pin configuration for HVQFN24 6.2 Pin description Table 2. ...
Page 8
NXP Semiconductors Table 2. Pin description …continued Symbol Pin TSSOP16 TSSOP24 HVQFN24 CS/ SI/ SCL/SCLK 5 12 SDA 6 13 IRQ 7 14 GPIO0 - 15 GPIO1 - 16 GPIO2 - 17 GPIO3 ...
Page 9
NXP Semiconductors [3] HVQFN24 package die supply ground is connected to both V ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal ...
Page 10
NXP Semiconductors Fig 8. 7.2.1 Auto RTS Figure 9 are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is ...
Page 11
NXP Semiconductors 7.2.2 Auto CTS Figure 10 sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the ...
Page 12
NXP Semiconductors There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Receiving any character will resume operation after recognizing the Xoff character possible that an Xon1 character is recognized as an ...
Page 13
NXP Semiconductors Fig 11. Example of software flow control SC16IS740_750_760_6 Product data sheet 2 Single UART with I C-bus/SPI interface, 64-byte FIFOs, IrDA SIR UART1 TRANSMIT FIFO data PARALLEL-TO-SERIAL Xoff–Xon–Xoff SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD compare Xoff2 WORD ...
Page 14
NXP Semiconductors 7.4 Hardware reset, Power-On Reset (POR) and software reset These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO ...
Page 15
NXP Semiconductors 7.5 Interrupts The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the IRQ signal in response to an ...
Page 16
NXP Semiconductors 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3: the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore not necessary to continuously ...
Page 17
NXP Semiconductors 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS740/750/760 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data ...
Page 18
NXP Semiconductors Figure 14 XTAL1 XTAL2 Fig 14. Prescaler and baud rate generator block diagram DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte ...
Page 19
NXP Semiconductors Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 Fig 15. Crystal oscillator circuit reference SC16IS740_750_760_6 Product data sheet 2 Single UART with I Baud ...
Page 20
NXP Semiconductors 8. Register descriptions The programming combinations for register selection are shown in Table 9. Register name Read mode RHR/THR IER IIR/FCR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL [3] IODir IOState IOIntEna IOControl EFCR DLL DLH ...
Page 21
Table 10. SC16IS740/750/760 internal registers Register Register Bit 7 Bit 6 address [1] General register set 0x00 RHR bit 7 bit 6 0x00 THR bit 7 bit 6 0x01 IER CTS RTS interrupt [2] interrupt enable [2] enable 0x02 FCR ...
Page 22
Table 10. SC16IS740/750/760 internal registers Register Register Bit 7 Bit 6 address [9] Special register set 0x00 DLL bit 7 bit 6 0x01 DLH bit 7 bit 6 [10] Enhanced register set 0x02 EFR Auto CTS Auto RTS 0x04 XON1 ...
Page 23
NXP Semiconductors 8.1 Receive Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX pin. The ...
Page 24
NXP Semiconductors [1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the XTAL1 clock. 8.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of ...
Page 25
NXP Semiconductors Table 13. LCR[ Table 14. LCR[ Table 15. LCR[ SC16IS740_750_760_6 Product data sheet Single UART with I LCR[5] parity selection LCR[4] LCR[3] Parity selection X 0 ...
Page 26
NXP Semiconductors 8.5 Line Status Register (LSR) Table 16 Table 16. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of ...
Page 27
NXP Semiconductors 8.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 17. Bit [1] MCR[7:5] and MCR[2] ...
Page 28
NXP Semiconductors 8.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the ...
Page 29
NXP Semiconductors 8.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of state from LOW to HIGH. The ...
Page 30
NXP Semiconductors 8.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 20. Bit 7:6 5:1 0 Table 21. Priority level ...
Page 31
NXP Semiconductors 8.10 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. the enhanced feature register bit settings. Table 22. Bit 3:0 8.11 Division registers (DLL, DLH) These are ...
Page 32
NXP Semiconductors 8.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. settings. Table 23. Bit 7:4 3:0 TCR trigger levels are available from 0 to ...
Page 33
NXP Semiconductors 8.15 Receiver FIFO Level register (RXLVL) This register is a read-only register, it reports the fill level of the receive FIFO. That is, the number of characters in the RX FIFO. Table 26. Bit 7 6:0 8.16 Programmable ...
Page 34
NXP Semiconductors 8.19 I/O Control register (IOControl) This register is only available on the SC16IS750 and SC16IS760. Table 30. Bit 7 Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled ...
Page 35
NXP Semiconductors 8.20 Extra Features Control Register (EFCR) Table 31. Bit [1] For SC16IS760 only. 9. RS-485 features 9.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR bit ...
Page 36
NXP Semiconductors 9.2 RS-485 RTS output inversion EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be sent it will deasserts the RTS pin ...
Page 37
NXP Semiconductors 2 10. I C-bus operation The two lines of the I lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique ...
Page 38
NXP Semiconductors SDA MSB SCL START condition 2 Fig 18. Data transfer on the I data output by transmitter data output by receiver SCL from master S START condition 2 Fig 19. Acknowledge on the I A ...
Page 39
NXP Semiconductors An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is transmitting (write) and a ...
Page 40
NXP Semiconductors master write: S SLAVE ADDRESS START condition master read: S SLAVE ADDRESS START condition combined S SLAVE ADDRESS formats: START condition read or 2 Fig 21. I C-bus data formats SC16IS740_750_760_6 Product data sheet Single UART with I ...
Page 41
NXP Semiconductors 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the ...
Page 42
NXP Semiconductors Table 33 SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I SPI interface to indicate a read or ...
Page 43
SCLK SI R CH1 CH0 X R A[3:0] = register address; CH1 = 0, CH0 = 0 a. Register write SCLK CH1 CH0 X R ...
Page 44
NXP Semiconductors Table 34. Bit 7 6:3 2:1 0 12. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot P/out T amb T j ...
Page 45
NXP Semiconductors 13. Static characteristics Table 36. Static characteristics V = 2 amb Symbol Parameter Supplies V supply voltage DD I supply current DD Inputs I2C/SPI, RX, ...
Page 46
NXP Semiconductors Table 36. Static characteristics V = 2 amb Symbol Parameter 2 I C-bus inputs SCL, CS/A0, SI/A1 V HIGH-level input voltage IH V LOW-level input ...
Page 47
NXP Semiconductors 14. Dynamic characteristics 2 Table 37. I C-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load 2 ...
Page 48
NXP Semiconductors RESET Fig 25. SCL delay after reset START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 26. I C-bus timing diagram SDA GPIOn Fig 27. Write ...
Page 49
NXP Semiconductors SLAVE ADDRESS SDA IRQ GPIOn Fig 29. GPIO pin interrupt (SC16IS750 and SC16IS760 only) RX IRQ Fig 30. Receive interrupt SLAVE ADDRESS SDA IRQ Fig 31. Receive interrupt clear SLAVE ADDRESS SDA IRQ Fig 32. Transmit interrupt clear ...
Page 50
NXP Semiconductors Table 38. f dynamic characteristics XTAL V = 2 amb Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f frequency on ...
Page 51
NXP Semiconductors Table 40. SC16IS760 SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load 2 ...
Page 52
NXP Semiconductors CS SCLK R/W GPIOx R A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0 Fig 35. SPI write IOState to GPIO switch (SC16IS750 and SC16IS760 only) CS SCLK SI A3 R/W DTR ...
Page 53
NXP Semiconductors CS SCLK R/W SO IRQ R A[3:0] = MSR (0x06); CH1 = 0; CH0 = 0 Fig 38. Read MSR to clear modem INT (SC16IS750 and SC16IS760 only) CS SCLK ...
Page 54
NXP Semiconductors 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. ...
Page 55
NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are ...
Page 56
NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...
Page 57
NXP Semiconductors 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering of SMD packages This text provides a ...
Page 58
NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities ...
Page 59
NXP Semiconductors Fig 44. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 43. Acronym CPU FIFO GPIO 2 I C-bus IrDA ...
Page 60
NXP Semiconductors 19. Revision history Table 44. Revision history Document ID Release date SC16IS740_750_760_6 20080513 • Modifications: Figure 24 “SPI operation” • Table 37 “I – added specification t – updated – • Figure 25 “SCL delay after reset” • ...
Page 61
NXP Semiconductors 20. Legal information 20.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
Page 62
NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...