M48T37 ST Microelectronics, M48T37 Datasheet - Page 11

• Manufacturer Part Number: M48T37
• Description: 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

Table 11. Register Map
Keys:
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ‘1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ‘1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
Address
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
S = Sign Bit
FT = Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to ’0’
BL = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits
RPT4
RPT3
RPT2
RPT1
WDS
WDF
AFE
D7
ST
W
0
0
0
0
0
BMB4
D6
FT
AF
R
0
0
0
0
0
0
1000 Year
10 Years
Alarm 10 Seconds
Alarm 10 Minutes
10 Seconds
10 Minutes
BMB3
AIarm 10 Hours
AIarm 10 Date
ABE
D5
0
0
S
Z
10 Hours
10 Date
BMB2
10 M
D4
BL
0
0
Data
BMB1
D3
0
0
Z
Calibration
Date: Day of Month
progress. Updating will resume within a second af-
ter the bit is reset to a ’0’.
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the
WRITE bit. Setting the WRITE bit to a ‘1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 11). Resetting the WRITE bit to
a ‘0’ then transfers the values of all time registers
(7FF1h, 7FF9h-7FFFh) to the actual TIMEKEEP-
ER counters and allows normal operation to re-
sume. After the WRITE bit is reset, the next clock
update will occur in approximately one second.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.
BMB0
Alarm Seconds
Alarm Minutes
D2
Alarm Hours
Alarm Date
Z
0
Seconds
100 Year
Minutes
Month
Hours
Year
Day of Week
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
AF = Alarm Flag
Z = ’0’ and are Read only
RB1
D1
Z
0
RB0
D0
Z
0
M48T37Y, M48T37V
Alarm Hour
Alarm Date
Alarm Sec
Watchdog
Alarm Min
Interrupts
Century
Control
Month
Flags
Date
Hour
Year
Functio n/Range
Day
Sec
Min
BCD Format
00-99
01-12
01-31
00-23
00-59
00-59
01-31
00-23
00-59
00-59
00-99
01-7
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