SAA7130 Philips Semiconductors, SAA7130 Datasheet
SAA7130
Available stocks
Related parts for SAA7130
SAA7130 Summary of contents
Page 1
... DATA SHEET SAA7130HL PCI video broadcast decoder Product specification INTEGRATED CIRCUITS 2002 Apr 23 ...
Page 2
... Apr 23 12 PACKAGE OUTLINE 13 SOLDERING 13.1 Introduction to soldering surface mount packages 13.2 Reflow soldering 13.3 Wave soldering 13.4 Manual soldering 13.5 Suitability of surface mount IC packages for wave and reflow soldering methods 14 DATA SHEET STATUS 15 DEFINITIONS 16 DISCLAIMERS 17 PURCHASE OF PHILIPS I 2 Product specification SAA7130HL 2 C COMPONENTS ...
Page 3
... SDK for Windows (95, 98, NT, 2000 and XP), Video for Windows (VfW) and Windows Driver Model (WDM). 2 GENERAL DESCRIPTION The SAA7130HL is a single chip solution to digitize and decode video, and capture it through the PCI-bus. Special means are incorporated to maintain the synchronization of audio to video. The device offers versatile peripheral interfaces (GPIO), that support various extended applications, e ...
Page 4
... Application diagram for capturing live TV video in the PC, with optional extensions for enhanced DTV and DVB capture. 2.1 Introduction The PCI video broadcast decoder SAA7130HL is a highly integrated, low cost and solid foundation for TV capture in the PC, for analog TV and digital video broadcast. The various multimedia data types are transported over the PCI-bus by bus-master-write, to optimum exploit the streaming capabilities of a modern host based system ...
Page 5
... TS GPIO static I/O pins interrupt input pins 2 I C-bus multi-master or slave video out Notes function available. 2. Dolby is a registered trademark of Dolby Laboratories Licensing Corporation. 2002 Apr 23 TV DECODER TYPE SAA7130HL SAA7133HL SAA7134HL SAA7135HL 2.2 2 kHz ...
Page 6
... PCI video broadcast decoder 2.3 Related documents This document describes the functionality and characteristics of the SAA7130HL. Other documents related to the SAA7130HL are: User manual SAA7130HL/34HL, describing the programmability Application note SAA7130HL/34HL, pointing out recommendations for system implementation Demonstration and reference boards, including description, schematics, etc.: – ...
Page 7
... FRONT-END ADC CV4 TS data TS PARALLEL TS data digital TS SERIAL 2 data I S inputs GPIO STATIC I/O interrupt IRQ SAA7130HL PIXEL ENGINE: DIGITAL VIDEO VIDEO • MATRIX COMB FILTER SCALER • GAMMA DECODER • FORMAT Fig.2 Block diagram. audio AUDIO stereo OUTPUT output PCI-bus REGISTER ...
Page 8
... Philips Semiconductors PCI video broadcast decoder 6 PINNING The SAA7130HL is packaged in a rectangular LQFP (low profile quad flat package) with 128 pins (see Fig.3). In Section 6.1 all the pins are sorted by number. The pin description for the functional groups is given in Tables ...
Page 9
... V SSD 100 101 102 103 104 105 106 9 Product specification SAA7130HL PIN 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 ...
Page 10
... LOW) stop input or output: target is requesting the master to stop the current transaction (active LOW) initialization device select input: this input is used to select the SAA7130HL during configuration read and write transactions device select input or output: driven by the target device, to acknowledge ...
Page 11
... V) not connected differential reference connection (for CV0 and CV1 supported with a capacitor analog ground (V analog ground composite video input (mode input (modes 6 and 8) analog supply voltage (3 Product specification SAA7130HL DESCRIPTION DESCRIPTION ) SSA ) SSA ...
Page 12
... AR CV3_C 118 AI V 119 AG SSA CV4 120 AI Note 1. The SAA7130HL offers an interface for analog video and audio signals. The related analog supply pins are included in this table. Table 5 JTAG test interface pins SYMBOL PIN TRST 121 I TCK 122 I TMS 123 ...
Page 13
... GIO GPIO0 Note 1. The SAA7130HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions can be selected: a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601); zoom-video, with discrete sync signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes. ...
Page 14
... PCI-bus); previous owner drives HIGH for one clock cycle before leaving to 3-state T/S 3-state I/O (for PCI-bus); bi-directional VG ground for digital supply VS supply voltage (3.3 V) With overscore or # this pin or ‘signal’ is active LOW, i.e. the function is ‘true’ if the logic level is LOW 2002 Apr 23 DESCRIPTION 2 C-bus interface; 3.3 and 5 V compatible, auto-adapting 14 Product specification SAA7130HL ...
Page 15
... STOP# 29 PERR# 30 SERR PAR CBE#1 33 AD15 34 AD14 35 AD13 36 AD12 37 V DDD 38 2002 Apr 23 SAA7130HL Fig.3 Pin configuration. 15 Product specification SAA7130HL n.c. 102 n.c. 101 RIGHT2 100 V REF0 99 RIGHT1 98 V SSA 97 96 LEFT1 V DDA 95 LEFT2 94 V SSD 93 V DDD 92 91 SDA 90 SCL ...
Page 16
... Philips Semiconductors PCI video broadcast decoder 7 FUNCTIONAL DESCRIPTION 7.1 Overview of internal functions The SAA7130HL is able to capture TV signals over the PCI-bus in personal computers by a single chip (see Fig.4). handbook, full pagewidth 5 analog video inputs INPUT SELECTION CLAMP AND GAIN CONTROL 9-BIT ADC 9-BIT ADC ...
Page 17
... Further analog video input signals, CVBS and/or Y-C, can be connected via the board back-panel, or the separate front connectors, e.g. from a camcorder. Accompanying stereo audio signals can also be fed to the SAA7130HL. Video is digitized and decoded to YUV. The digital streams are pumped via DMA into the PCI memory space. ...
Page 18
... DMA MASTER 2 I C-BUS EEPROM INTO PCI SYSTEM VENDOR ID SAA7130HL PCI-bus: digital video, raw VBI, TS NORTH BRIDGE ISA FSB Fig.5 TV mono capture card. 18 Product specification SAA7130HL analog audio cable SOUND CARD AGP VGA AND LOCAL MEMORY CPU AND CACHE MEMORY MHC172 ...
Page 19
... IF-PLL can be routed to one of the video inputs and the audio (left or right) input of the SAA7130HL for analog video decoding and direct audio streaming to the sound card. On the other hand, the 2nd IF signal of the digital IF-PLL is fed directly ...
Page 20
... Software support 7.3.1 D EVICE DRIVER A complex and powerful software packet is provided for the SAA7130HL. This packet includes plug-and-play driver and capture driver installations for all commonly used 32-bit Windows platforms. All platform related drivers support the following: Video preview and capture interfaces ...
Page 21
... Windows operating systems in the same way. The SDK for the SAA7130HL contains the detailed description of all software components such as API documentation for streaming, tuner control, dialogues and direct draw control. ...
Page 22
... PCI interface 7.4.1 PCI CONFIGURATION REGISTERS The PCI interface of the SAA7130HL complies with the “PCI specification 2.2” and supports power management and Advanced Configuration and Power Interface (ACPI) as required by the “PC Design Guide 2001” . The PCI specification defines a structure of the PCI configuration space that is investigated during the boot-up of the system ...
Page 23
... D3-hot. D1 First step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. Most of the circuitry of the SAA7130HL is disabled with exception of the crystal and real-time clock oscillators, so that a quick recovery from possible. ...
Page 24
... ADDRESS SPACE) page table 000H 00001000H 00008000H 00009000H 0000A000H 0000D000H 00011000H 00014000H 007H 00016000H 0001E000H 015H 24 Product specification SAA7130HL real-time streams FIFO POOL DMA ADDRESS GENERATION VIRTUAL TO PHYSICAL ADDRESS TRANSLATION PCI TRANSFER AND CONTROL physical address space on PCI MHB996 ...
Page 25
... Tables list some characteristics of the various TV standards. The SAA7130HL decodes all colour TV standards and non-standard signals as generated by video tape recorders e.g. automatic video standard detection can be applied, with preference options for certain standards, or the decoder can be forced to a dedicated standard ...
Page 26
... USA, South Japan part of Europe, Korea part of Europe, China America 26 Product specification SAA7130HL SECAM LDGHK 50 625 4.406 4.250 282 272 France, Eastern Europe, transcoding Africa, Middle East NTSC-tape DIGITAL CODING ...
Page 27
... LOCKED CLOCK filtering further minimizes colour crosstalk artifacts, which would otherwise produce erroneous colours on detailed luminance structures. The comb filter as implemented in the SAA7130HL is adaptive in two ways: Adaptive to transitions in the picture content Adaptive to non-standard signals (e.g. VCR). The integrated digital delay lines are always exactly correct, due to the applied unique line-locked sampling scheme (LLC) ...
Page 28
... Philips Semiconductors PCI video broadcast decoder 7.6.6 V IDEO SCALING The SAA7130HL incorporates a filter and processing unit to downscale or upscale the video picture in the horizontal and vertical dimension, and in frame rate (see Figs 11 and 12). The phase accuracy of the 1 re-sampling process is of the original sample distance. ...
Page 29
... FID = 0) sample rate 4th field (even, FID = 1) sample rate scaling Fig.12 Scaler task processing with DMA interfacing. 29 Product specification SAA7130HL VBI DMA 1st buffer (A) 2nd buffer (A) 3rd buffer (B) 4th buffer (B) video DMA (A) e.g. interlaced 1st buffer (upper field) ...
Page 30
... The SAA7130HL offers a multitude of formats to write video streams over the PCI-bus: YUV and RGB colour space, 15-bit, 16-bit, 24-bit and 32-bit representation, packed and planar formats. For legacy requirements (VfW) a clipping procedure is implemented, that allows the definition of 8 overlay rectangles ...
Page 31
... U output range ( accordance with ITU-R BT.601 255 white 199 black black shoulder 60 1 sync bottom b. Sources not containing black 31 Product specification SAA7130HL 255 240 red 100% red 75% 212 colourless 128 V-COMPONENT cyan 75% 44 cyan 100 MGC634 ). ...
Page 32
... Feeding video stream to a local MPEG compression device on the same PCI board, e.g. for time shift viewing applications. The video port of the SAA7130HL supports the following 8 and 16-bit wide YUV video signalling standards (see Table 7): VMI: 8-bit wide data stream, clocked by LLC = 27 MHz, ...
Page 33
... TV broadcast reception usually provides a DTV signal on low IF, i.e. downconverted into a frequency range from MHz. Such signals can be fed to one of the 5 video inputs of the SAA7130HL for digitizing. The digital raw DTV is output at the video port, and is sent to the peripheral channel decoder, e.g. TDA8961 for VSB-8 decoding ...
Page 34
... Philips Semiconductors PCI video broadcast decoder 8 BOUNDARY SCAN TEST The SAA7130HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7130HL follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture” ...
Page 35
... Apr 23 CONDITIONS MIN. 0.5 0.5 0.5 0.5 outputs in 3-state 0.5 outputs in 3-state; 0.5 3.0 V < V < 3.6 V DDD 65 0 note 1 250 note 2 3500 CONDITIONS in free air 35 Product specification SAA7130HL MAX. UNIT +4.6 V +4.6 V 100 mV +4 0.5 V DDD +4.6 V +5.5 V +150 +200 V +3500 V VALUE UNIT 34 ...
Page 36
... D0 after reset D1 D2 D3-hot crystal 1; see Table 16 crystal 2; see Table 2.7 V; note 0.5 V; note 2 mA; note 0.4 to 2.4 V; note 3 1 2.4 to 0.4 V; note Product specification SAA7130HL MIN. TYP. MAX. 3.3 3.6 3.3 3.6 1.0 0.1 0.2 0.1 0.02 32.11 24.576 32.11 33 0.5 100 V + 0.3 DDD 0.3 +0.8 5.75 0.5 +0 ...
Page 37
... ADC only; note 10 amplifier plus anti-alias filter bypassed amplifier plus anti-alias filter bypassed MHz; anti-alias filter i bypassed; AGC = MHz; anti-alias filter i bypassed; AGC = Product specification SAA7130HL TYP. MAX 400 kbits/s +0 ...
Page 38
... GPIO27, TDI, TDO, TMS, TCK TO 3.3 V signal levels at V 3.3 V DDD I/O at high-impedance DDD V_CLK (see Fig.18) LLC active LLC2 active 38 Product specification SAA7130HL MIN. TYP. MAX. 200 145 48 150 250 375 0.1 0 TRST AND 2 ...
Page 39
... ON PIN 0.4 to 2.4 V 2.4 to 0.4 V ADC_CLK inverted and not delayed; note 14 inverted and not delayed; notes 14 and 16 GPIO20 (see Fig.19) note 13 0.8 to 2.0 V 2 Product specification SAA7130HL MIN. TYP. MAX GPIO17, GPIO22 GPIO23 (see Fig.18) TO AND ...
Page 40
... See also application notes SAA7130HL/34HL. 10. See the user manuals of the SAA7130HL/34HL for Anti-Alias Filter (AAF). 11. Definition of levels and level setting: a) The full-scale level for analog audio signals V is defined (FS) ...
Page 41
... Signal V_CLK inverted; not delayed (programming register vp_clk_ctr ADC_CLK handbook, full pagewidth CLK OUTPUT DELAY 3-STATE OUTPUT INPUT 2002 Apr ns). ADC_CLK 1 val 1 off 1.5 V input valid 1.5 V Fig.17 PCI I/O timing. 41 Product specification SAA7130HL 2.4 V 0.4 V 2.4 V 0.4 V MGG280 ...
Page 42
... GPIO0 to GPIO 7, GPIO 16, GPIO19 and GPIO21) TS_CLK (pin GPIO20 ) 2002 Apr su( Fig.19 Data input timing (TS data and control inputs). 42 Product specification SAA7130HL h( 2.4 V 0.4 V 2.4 V 1.5 V 0.4 V MHC002 2.0 V 0.8 V 2.0 V 1.5 V 0.8 V ...
Page 43
... External components Typical load 33 capacitance at pin XTALI Typical load 33 capacitance at pin XTALO Typical capacitance of n.a. LC filter Typical inductance of n.a. LC filter Note 1. For oscillator application, see the application notes of the SAA7130HL/34HL. 2002 Apr 23 CRYSTAL FREQUENCY 32.11 MHz 3rd HARMONIC 13.5 1 4.3 6 ...
Page 44
... 0.27 0.20 20.1 14.1 22.15 0.5 0.17 0.09 19.9 13.9 21.85 REFERENCES JEDEC EIAJ MS-026 detail 16.15 0.75 1.0 0.2 0.12 0.1 15.85 0.45 EUROPEAN PROJECTION Product specification SAA7130HL SOT425 (1) ( 0.81 0. 0.59 0.59 0 ISSUE DATE 99-12-27 00-01-19 ...
Page 45
... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 45 Product specification SAA7130HL ...
Page 46
... This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. 46 Product specification SAA7130HL SOLDERING METHOD WAVE REFLOW suitable (2) suitable ...
Page 47
... Philips Semiconductors sales office or e-mail: licensing.cip@philips.com. C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 47 Product specification SAA7130HL Philips Semiconductors Use of this product patent to use the 2 C specification defined by ...
Page 48
... Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. ...