SAA7130 Philips Semiconductors, SAA7130 Datasheet - Page 23

• Manufacturer Part Number: SAA7130
• Description: PCI video broadcast decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 11 Power management table
7.4.3
The SAA7130HL supports seven DMA channels to
master-write captured active video, raw VBI and DTV/DVB
Transport Streams (TS) into the PCI memory. Each DMA
channel contains inherently the definition of two buffers,
e.g. for odd and even fields in case of interlaced video.
The DMA channels share in time and space one common
FIFO pool of 256 Dwords (1024 bytes) total. It is freely
configurable how much FIFO capacity can be associated
with which DMA channel. Furthermore, a preferred
minimum burst length can be programmed, i.e. the amount
of data to be collected before the request for the PCI-bus
is issued. This means that latency behaviour per DMA
channel can be tailored and optimized for a given
application.
In the event that a FIFO of a certain channel overflows due
to latency conflict on the bus, graceful overflow recovery is
applied. The mount of data that gets lost because it could
not be transmitted, is monitored (counted) and the PCI-bus
address pointer is incremented accordingly. Thus new
data will be written to the correct memory place, after the
latency conflict is resolved.
7.4.4
Most operating systems allocate memory to requesting
applications for DMA as continuous ranges in virtual
address space. The data flow over the PCI-bus points to
physical addresses, usually not continuous and split in
pages of 4 kbytes (Intel architecture, most UNIX systems,
Power PC).
2002 Apr 23
D0
D1
D2
D3-hot
POWER STATE
PCI video broadcast decoder
DMA
V
IRTUAL AND PHYSICAL ADDRESSING
AND CONFIGURABLE
Normal operation: all functions accessible and programmable. The default setting after reset and
before driver interaction (D0 un-initialized) switches most of the circuitry of the SAA7130HL into
the power-down mode, effectively such as D3-hot.
First step of reduced power consumption: no functional operation; program registers are not
accessible, but content is maintained. Most of the circuitry of the SAA7130HL is disabled with
exception of the crystal and real-time clock oscillators, so that a quick recovery from D1 to D0 is
possible.
Second step of reduced power consumption: no functional operation; program registers are not
accessible, but content is maintained. All functional circuitry of the SAA7130HL is disabled,
including the crystal and clock oscillators.
Lowest power consumption: no functional operation. The content of the programming registers
gets lost and is set to default values when returning to D0.
FIFO
23
The association between the virtual (logic) address space
and the fragmented physical address space is defined in
page tables (system files); see Fig.10.
The SAA7130HL incorporates hardware support (MMU) to
translate virtual to physical addresses on the fly, by
investigating the related page table information. This
hardware support reduces the demand for real-time
software interaction and interrupt requests, and therefore
saves system resources.
7.4.5
The SAA7130HL provides a set of status information
about internal signal processing, video standard detection,
peripheral inputs and outputs (pins GPIO) and behaviour
on the PCI-bus. This status information can be
conditionally enabled to raise an interrupt on the PCI-bus,
e.g. completion of a certain DMA channel or buffer, or
change in a detected TV standard, or the state of
peripheral devices.
The cause of an issued interrupt is reported in a dedicated
register, even if the original condition has changed before
the system was able to investigate the interrupt.
DESCRIPTION
S
TATUS AND INTERRUPTS ON
SAA7130HL
PCI-
Product specification
BUS