SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 32

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.4
The interrupt system in the SAA7391 is intended to make it possible to acknowledge interrupts both independently
without interference or together. There are two interrupt pins to the sub-CPU from the SAA7391. The INT pin is
associated only with the host interface register IFSTAT (address FF92H). The INT2 pin is associated with 6 interrupt
registers which cover the SAA7391 drive block and UART. Two status/reset registers and two interrupt enable register
for the drive block and one status/reset register plus an interrupt enable register for the UART.
Table 44 IFSTAT interrupt register for the host interface; address FF92H (note 1)
Note
1. Interrupt status bits are described in the host interface; see Section 7.5.3.18.
7.4.1
By writing a logic 1 to the INT1RESET register the bits will negate the INT1STATUS register bits. Writing a logic 1 to an
INT1ENABLE bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
Table 45 INT1STATUS: drive interrupt register status; address FF7AH (see Table 54)
Table 46 INT1RESET: drive interrupt register reset; address FF7AH (see Table 54)
7.4.1.1
Table 47 INT1ENABLE: drive interrupt register enable; address FF7BH (see Table 54)
1997 Aug 01
ACCESS
ACCESS
ACCESS
ACCESS
ATAPI CD-R block encoder/decoder
W
W
R
R
Interrupt registers
I
NTERRUPT
INT1ENABLE: drive interrupt register enable bits
BIT 7
BIT 7
BIT 7
BIT 7
cmdi
dec
dec
dec
1
BIT 6
BIT 6
nocor
BIT 6
nocor
BIT 6
nocor
dtei
erablk
erablk
erablk
BIT 5
BIT 5
BIT 5
BIT 5
drqi
ultra_stop
BIT 4
BIT 4
BIT 4
BIT 4
cblk
cblk
cblk
32
uceblk
uceblk
uceblk
dtbsy
BIT 3
BIT 3
BIT 3
BIT 3
crc-ng
crc-ng
crc-ng
BIT 2
BIT 2
BIT 2
BIT 2
srsti
reset08
BIT 1
BIT 1
BIT 1
BIT 1
Objective specification
q-ng
q-ng
q-ng
SAA7391
crc_error
a0comp/
BIT 0
BIT 0
BIT 0
BIT 0
int2
int2