SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 46

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.5.3.22
The ‘ultractrl’ register bits can be used to add system clock
cycles to various timing limits used in the host interface
ultra DMA transfer engine.
This enables the SAA7391 to meet ultra DMA Mode 0
timings when the SAA7391 system clock is higher than
33.8688 MHz.
7.5.3.23
Table 76 HISEQ: host interface sequencer register; address FF96H (see Table 77)
Table 77 Description of the HISEQ register bits
1997 Aug 01
ACCESS
ATAPI CD-R block encoder/decoder
RW
BIT
7
6
5
4
3
2
Description of the ultra control bits
HISEQ
repeat autoa0
autoa0
BIT 7
sus_seq
autodrq
autoa0
NAME
comp
error
autodrq
BIT 6
automatic A0 packet transfer enable: this bit enables the sequencer to automatically
handle transfer of A0 packet bytes
enables the auto data request sequence: this bit enables automatic handling of data
requests in PIO and DMA mode transfers
Completion sequence for ‘autodrq’: this bit indicates that the auto completion sequence
should be performed after the last data transfer. This bit is only valid when the auto
sequencer is enabled.
completion sequence with error status: this bit is copied to the check bit of the ASTAT
register just before an auto completion sequence is performed
Suspend auto sequence: this bit suspends the auto sequencer for debug. If the
suspend state is a write to register state then the write operation will only take place
when after the ‘sus_seq’ bit is negated.
Repeat the A0 packet reception auto sequence after an ‘autodrq’ or auto completion
sequence. This bit, if set before an ‘autodrq’ or auto completion sequence, will be
copied to ‘autoa0’ bit when the sequencer is reset at the end of an ‘autodrq’ or auto
completion sequence. This bit is negated at the end of the ‘autoA0’ sequence. Its effect
is to repeat the ‘autoA0’ sequence one more time only. It should be noted that this bit is
only available on RODAP and not the M1 data base.
autoa0 = 1; enables automatic transfer of A0 packet bytes
autoa0 = 0; disables automatic transfer of A0 packet bytes
autodrq = 1; auto sequencer is enabled to perform auto data requests
autodrq = 0; auto sequencer is not enabled to perform auto data request
comp = 1; enable the auto sequencer to automate the completion sequence
comp = 0; disable the auto completion sequence
error = 1; completion sequence with error status in check bit of ASTAT
error = 0; completion without error status
sus_seq = 1; suspend sequencer in present state
sus_seq = 0; normal sequence operation
repeat autoa0 = 1; repeat ‘autoA0’ sequencer after ‘autodrq’ or auto completion
repeat autoa0 = 0; no effect
BIT 5
comp
BIT 4
error
46
When the SAA7391 system clock is 33.8688 MHz,
maximum data transfer rates in ultra DMA Mode 0 are
achieved by setting ‘ultractrl’ to (0001).
For information on meeting Mode 0 timings for system
clocks other than 33.8688 MHz, please consult the user
manual or product support.
sus_seq
BIT 3
DESCRIPTION
repeat autoa0
BIT 2
Objective specification
BIT 1
SAA7391
BIT 0