SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 33

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SAA7391H

Manufacturer Part Number
SAA7391H
Description
ATAPI CD-R block encoder/decoder
Manufacturer
Philips Semiconductors
Datasheet

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Philips Semiconductors
7.4.2
By writing a logic 1 to INT2RESET register bits will negate the INT2STATUS bit. Writing a logic 1 to an INT2ENABLE bit
will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
Table 48 INT2STATUS: drive interrupt register status; address FF7CH (see Table 54)
Table 49 INT2RESET: drive interrupt register reset; address FF7CH (see Table 54)
Table 50 INT2ENABLE: drive interrupt register enable; address FF7DH (see Table 54)
7.4.3
By writing a logic 1 to the INT2RESET register bits will negate the INT2STATUS bit. Writing a logic 1 to an INT2ENABLE
bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
The INT2 interrupt corresponds to not (INT1 or INT2 or UARTINT).
Table 51 UARTINTSTATUS: UART interrupt register status; address FF78H (see Table 54)
Table 52 UARTINTRESET: UART interrupt register reset; address FF78H (see Table 54)
Table 53 UARTINTENABLE: UART interrupt register enable; address FF79H (see Table 54)
1997 Aug 01
ACCESS
ACCESS
ACCESS
ACCESS
ACCESS
ACCESS
ATAPI CD-R block encoder/decoder
W
W
R
W
W
R
I
UART
NTERRUPT
comsync
comsync
comsync
countzero
countzero
countzero
hostbyte
hostbyte
hostbyte
INTERRUPT
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
2
syssync
syssync
syssync
BIT 6
BIT 6
BIT 6
reload
reload
reload
BIT 6
BIT 6
BIT 6
drive
drive
drive
notcomsync
notcomsync
notcomsync
countzero
countzero
countzero
BIT 5
BIT 5
BIT 5
hostrel
hostrel
hostrel
BIT 5
BIT 5
BIT 5
notsyssync
notsyssync
notsyssync
copyend
copyend
copyend
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
33
nottxbfull
nottxbfull
nottxbfull
subcode
subcode
subcode
syncint
syncint
syncint
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
dmatxint
dmatxini
dmatxini
rxbfull
rxbfull
rxbfull
BIT 2
BIT 2
BIT 2
BIT 2
BIT 2
BIT 2
overrun
overrun
overrun
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
Objective specification
int1
SAA7391
rxparity
rxparity
rxparity
uartint
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0

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