SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 65

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SAA7391H

Manufacturer Part Number
SAA7391H
Description
ATAPI CD-R block encoder/decoder
Manufacturer
Philips Semiconductors
Datasheet

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Philips Semiconductors
Table 101 Description of the CLK_CON register bits
Table 102 The relationship between the values of the
1997 Aug 01
ATAPI CD-R block encoder/decoder
1 and 0
BIT
7
6
m6 to m0
m bits and VCO frequency for a normalised
PLL frequency of 500 kHz; note 1
(HEX)
4C
0B
2E
5D
3A
6B
2D
5B
6C
02
04
08
22
44
09
13
26
18
31
62
45
17
75
56
36
11
xtal1 and
NAME
pllpwr
pllena
xtal0
VALUE
00
01
10
11
FREQUENCY (MHz)
0
1
0
1
PLL is powered-down
PLL is powered-up
system clock source is CRIN
system clock source is from clock multiplier
crystal is 8.4672 MHz; divide-by-16
crystal is 11.289 MH; divide-by-22
crystal is 16.9344 MHz; divide-by-32
crystal is 33.8688 MHz; divide-by-64
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
3
4
5
6
7
8
9
65
DESCRIPTION
m6 to m0
(HEX)
0C
4D
1A
6A
4E
1C
1E
3D
58
30
60
41
03
06
19
33
66
35
54
29
53
27
39
73
67
4F
FREQUENCY (MHz)
529.2
513.1
529.2
529.2
f
PLL
Objective specification
(kHz)
SAA7391
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
default
default
default
NOTES

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