AD7910ARM-REEL AD [Analog Devices], AD7910ARM-REEL Datasheet

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AD7910ARM-REEL

Manufacturer Part Number
AD7910ARM-REEL
Description
250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70
Manufacturer
AD [Analog Devices]
Datasheet
GENERAL DESCRIPTION
The AD7910/AD7920 are, respectively, 10-bit and 12-bit, high
speed, low power, successive-approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7910/AD7920 use advanced design techniques to achieve
very low power dissipation at high throughput rates.
*Protected by U.S.Patent No. 6,681,332.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
Throughput Rate: 250 kSPS
Specified for V
Low Power:
Wide Input Bandwidth:
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
Standby Mode: 1 A Max
6-Lead SC70 Package
8-Lead MSOP Package
APPLICATIONS
Battery-Powered Systems
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors
3.6 mW Typ at 250 kSPS with 3 V Supplies
12.5 mW Typ at 250 kSPS with 5 V Supplies
71 dB SNR at 100 kHz Input Frequency
Personal Digital Assistants
Medical Instruments
Mobile Communications
SPI
®
/QSPI™/MICROWIRE™/DSP Compatible
DD
of 2.35 V to 5.25 V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
10-/12-Bit ADCs in 6-Lead SC70
The reference for the part is taken internally from V
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to V
is determined by the SCLK.
PRODUCT HIGHLIGHTS
1. 10-/12-Bit ADCs in SC70 and MSOP Packages.
2. Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
4. Reference Derived from the Power Supply.
5. No Pipeline Delay.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption to
be reduced when power-down mode is used while not convert-
ing. The part also features a power-down mode to maximize
power efficiency at lower throughput rates. Current consumption
is 1 A max and 50 nA typically when in power-down mode.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
V
IN
FUNCTIONAL BLOCK DIAGRAM
T/H
© 2004 Analog Devices, Inc. All rights reserved.
AD7910/AD7920
APPROXIMATION
AD7910/AD7920
SUCCESSIVE-
10-/12-BIT
CONTROL
LOGIC
V
ADC
GND
DD
DD
. The conversion rate
250 kSPS,
www.analog.com
SCLK
SDATA
CS
DD.
This
*

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AD7910ARM-REEL Summary of contents

Page 1

FEATURES Throughput Rate: 250 kSPS Specified for Low Power: 3.6 mW Typ at 250 kSPS with 3 V Supplies 12.5 mW Typ at 250 kSPS with 5 V Supplies Wide Input Bandwidth: ...

Page 2

AD7910–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 3 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential ...

Page 3

AD7920–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Signal-to-Noise Ratio (SNR) 3 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 3 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY ...

Page 4

AD7910/AD7920 AD7920–SPECIFICATIONS Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode 7 Power Dissipation Normal Mode (Operational) Full Power-Down NOTES 1 Temperature range from –40∞C to +85∞C. 2 Operational from V = 2.0 ...

Page 5

I 200 OUTPUT PIN C L 50pF I 200 A OH Figure 1. Load Circuit for Digital Output Timing Specifications SCLK SDATA Z ZERO ZERO THREE- 4 LEADING ZEROS STATE ...

Page 6

... AD7910AKS-REEL –40∞C to +85∞C AD7910AKS-REEL7 –40∞C to +85∞C AD7910ARM –40∞C to +85∞C AD7910ARM-REEL –40∞C to +85∞C AD7910ARM-REEL7 –40∞C to +85∞C AD7920AKS-500RL7 –40∞C to +85∞C AD7920AKS-REEL –40∞C to +85∞C AD7920AKS-REEL7 –40∞C to +85∞C AD7920BKS – ...

Page 7

SC70 GND (Not to Scale) Mnemonic Function CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7910/ AD7920 and framing the serial data ...

Page 8

AD7910/AD7920 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7920 and AD7910, the endpoints of the transfer function are zero scale, a point 1 LSB below the ...

Page 9

TPC 1 and TPC 2 show a typical FFT plot for the AD7920 and AD7910, respectively 250 kSPS sampling rate and a 100 kHz input frequency. TPC 3 shows the signal-to-(noise + distortion) ratio performance versus input frequency ...

Page 10

AD7910/AD7920 1 2.35V 0.8 DD TEMP = 250kSPS 0.6 SAMPLE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 CODE TPC 5. AD7920 DNL Performance – 3.6V ...

Page 11

When the ADC starts a conversion (see Figure 5), SW2 opens and SW1 moves to position B, causing the comparator to become unbalanced. The control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge ...

Page 12

AD7910/AD7920 Analog Input Figure 8 shows an equivalent circuit of the analog input structure of the AD7910/AD7920. The two diodes D1 and D2 provide ESD protection for the analog input. Care must be taken to ensure that the analog input ...

Page 13

Power-Down Mode This mode is intended for use in applications where slower through- put rates are required; either the ADC is powered down between conversions series of conversions may be performed at a high throughput rate and the ...

Page 14

AD7910/AD7920 the first SCLK edge the part receives after the falling edge of CS. This is shown as point A in Figure 11. Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire ...

Page 15

SCLK SDATA Z ZERO ZERO THREE- 4 LEADING ZEROS STATE SCLK ZERO ZERO SDATA 4 LEADING ZEROS THREE-STATE SERIAL INTERFACE Figures 13 and 14 show ...

Page 16

AD7910/AD7920 MICROPROCESSOR INTERFACING The serial interface on the AD7910/AD7920 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7910/AD7920 with some of the more common microcontroller and DSP serial ...

Page 17

AD7910/AD7920 to DSP563xx Interface The diagram in Figure 17 shows how the AD7910/AD7920 can be connected to the SSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. The SSI is operated in Synchronous and Normal mode (SYN ...

Page 18

AD7910/AD7920 As can be seen in Figure 18, for the MSOP package the decou- pling capacitor has been placed as close as possible to the IC, with short track lengths to V and GND pins. The decoupling capaci- DD tor ...

Page 19

Thin Shrink Small Outline Transistor Package [SC70] 1.25 BSC 1.00 0.90 0.70 0.10 MAX REV. B OUTLINE DIMENSIONS (KS-6) Dimensions shown in millimeters 2.00 BSC 2.10 BSC PIN 1 0.65 BSC 1.30 BSC ...

Page 20

AD7910/AD7920 Revision History Location 3/04 – Data Sheet changed from REV REV. B Added U.S. Patent number . . . . . . . . . . . . . . . . . . . . . ...

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