AD7910 Analog Devices, AD7910 Datasheet
AD7910
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AD7910 Summary of contents
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... DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with the part. The AD7910/AD7920 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from V allows the widest dynamic input range to the ADC ...
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... Serial Interface ................................................................................ 19 Microprocessor Interfacing........................................................... 20 AD7910/AD7920 to TMS320C541 Interface ......................... 20 AD7910/AD7920 to ADSP-218x.............................................. 20 AD7910/AD7920 to DSP563xx Interface ............................... 21 Application Hints ........................................................................... 22 Grounding and Layout .............................................................. 22 Evaluating Performance ............................................................ 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 24 8/03—Rev Rev. A Changes to Ordering Guide.............................................................6 Changes to Evaluating the AD7910/AD7920 Performance Section.............................................................................................. 18 Updated Outline Dimensions ...................................................... 19 Rev Page ...
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... V min/max 2.5 mA typ 1.2 mA typ 3 mA max 1.4 mA max 1 μA max Rev Page AD7910/AD7920 Test Conditions/Comments f = 100 kHz sine wave 100.73 kHz 90.7 kHz fa = 100.73 kHz 90.7 kHz @ 0.1 dB Guaranteed no missed codes to 10 bits Track-and-hold in track typ when in hold ...
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... AD7910/AD7920 1 Parameter 6 Power Dissipation Normal Mode (Operational) Full Power-Down 1 Temperature range from −40°C to +85°C. 2 Operational from V = 2.0 V, with input high voltage ( See the Terminology section. 4 SC70 values guaranteed by characterization. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. AD7920 ...
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... V max. INL = 4. 5. Rev Page AD7910/AD7920 Test Conditions/Comments Typically 10 nA 200 μ 2. 5.25 V SOURCE 200 μA ...
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... See Power-Up Time section. , unless otherwise noted. Unit Description kHz min 3 MHz max AD7910 AD7920 ns min Minimum quiet time required between bus relinquish and start of next conversion ns min Minimum CS pulse width ns min CS to SCLK setup time ns max Delay from CS until SDATA three-state disabled ...
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... Figure 3. AD7920 Serial Interface Timing Diagram t CONVERT 12.5(1/f ) SCLK 1/THROUGHPUT Figure 4. Serial Interface Timing Example Rev Page AD7910/AD7920 = 3.4 MHz and a throughput rate of SCLK + 12.5(1/f 2 SCLK = 10 ns min, this leaves 2.97 μs. This 2.97 μs 2 ACQ . From Figure 4, t ACQ ) + max ...
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... AD7910/AD7920 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to GND DD Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies Operating Temperature Range Commercial (A, B Grade) Storage Temperature Range Junction Temperature MSOP Package θ ...
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... The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7920 consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. The data stream from the AD7910 consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros, which is also provided MSB first. ...
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... AD7910/AD7920 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7 and Figure 8 show a typical FFT plot for the AD7920 and AD7910, respectively 250 kSPS sampling rate and a 100 kHz input frequency. Figure 9 shows the signal-to-(noise + distortion) ratio performance vs. input frequency for various supply voltages while sampling at 250 kSPS with an SCLK frequency of 5 MHz for the AD7920 ...
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... INPUT FREQUENCY (kHz) Figure 12. THD vs. Analog Input Frequency for Various Source Impedances –65 –70 –75 –80 –85 –90 3072 3584 4096 Figure 13. THD vs. Analog Input Frequency for Various Supply Voltages = 0Ω 1000 Rev Page AD7910/AD7920 V = 2.35V 4.75V 3. 2. 5.25V ...
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... The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7920 and AD7910, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. ...
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... The AD7910/AD7920 are fast, micropower, 10-bit/12-bit, single-supply A/D converters, respectively. The parts can be operated from a 2. 5.25 V supply. When operated from either supply supply, the AD7910/AD7920 are capable of throughput rates of 250 kSPS when provided with a 5 MHz clock. ...
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... This corresponds to a 0.057 LSB error for the AD7920 with from the REF193 and a 0.014 LSB error for the AD7910. For applications where power consumption is of concern, the power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance ...
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... ANALOG INPUT Figure 18 shows an equivalent circuit of the analog input structure of the AD7910/AD7920. The two diodes, D1 and D2, provide ESD protection for the analog input. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting current into the substrate ...
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... SDATA goes back into three-state. For the AD7920, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7910, a minimum of 14 serial clock cycles is required to complete the conversion and access the complete conversion result. CS can idle high until the next conversion or can idle low until CS returns high sometime prior to the next conversion, effectively idling CS low ...
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... A 1 SCLK SDATA When power supplies are first applied to the AD7910/AD7920, the ADC can power up in either power-down mode or in normal mode. Because of this best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if the intention is to keep the part in power- ...
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... down mode between conversions, the power dissipation during normal operation is 4.2 mW. Assuming the same timing conditions as before, the AD7910/AD7920 can now be said V). DD dissipate 4.2 mW for 6 μs during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated during each cycle is (6/10) × ...
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... Figure 23. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7920. For the AD7910, the conversion requires 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, track-and- hold goes back into track on the next SCLK rising edge, as shown in Figure 24 at Point B ...
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... For the AD7920, the word length should be set to 16 bits ( the SPC register). This DSP allows frames with a word length of 16 bits or 8 bits. Therefore, in the case of the AD7910 where just 14 bits could be required, the FO bit would be set bits also ...
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... WL1 = 1, and WL0 = 0 for the AD7920. This DSP does not offer the option for a 14-bit word length, so the AD7910 word length is set to 16 bits like the AD7920. For the AD7910, the conversion process uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word ...
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... A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7910/AD7920 system where multiple devices require an AGND to DGND connection then the connection should still be made at one point only, a star ground point that should be established as close to the AD7910/AD7920 as possible ...
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... COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 30. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 3.20 3.00 2.80 5. 3.20 4.90 3.00 4.65 2. PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.15 0.38 0.23 0.00 0.22 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 31. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev Page AD7910/AD7920 0.46 0.36 0.22 0.26 0.08 0.80 8° 0.60 0° 0.40 ...
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... AD7910AKSZ-500RL7 −40°C to +85°C 2 AD7910AKSZ-REEL −40°C to +85°C 2 AD7910AKSZ-REEL7 −40°C to +85°C AD7910ARM −40°C to +85°C AD7910ARM-REEL −40°C to +85°C AD7910ARM-REEL7 −40°C to +85°C 2 AD7910ARMZ −40°C to +85°C AD7920AKS-500RL7 −40°C to +85°C AD7920AKS-REEL − ...