AD7910ARM-REEL AD [Analog Devices], AD7910ARM-REEL Datasheet - Page 5

• Manufacturer Part Number: AD7910ARM-REEL
• Description: 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70
• Manufacturer: AD [Analog Devices]

Timing Example 2
The AD7920 can also operate with slower clock frequencies.
From Figure 3, having f
of 150 kSPS gives a cycle time of t
6.66 ms. With t
2.97 ms satisfies the requirement of 250 ns for t
Figure 3, t
REV. B
Figure 1. Load Circuit for Digital Output Timing
Specifications
SDATA
SCLK
SCLK
ACQ
CS
CS
TO OUTPUT
comprises 2.5(1/f
2
THREE-
STATE
= 10 ns min, this leaves t
PIN
t
t
2
2
Z
50pF
SCLK
1
1
t
C
3
ZERO
L
4 LEADING ZEROS
= 3.4 MHz and a throughput rate
200 A
200 A
SCLK
2
2
ZERO
2
) + t
+ 12.5(1/f
I
I
OL
OH
3
8
Figure 2. AD7920 Serial Interface Timing Diagram
3
ACQ
ZERO
+ t
t
4
12.5(1/f
QUIET
Figure 3. Serial Interface Timing Example
to be 2.97 ms. This
SCLK
1.6V
4
ACQ
4
DB11
SCLK
, t
) + t
. From
t
8
6
t
)
= 36 ns
CONVERT
5
t
5
ACQ
CONVERT
t
DB10
7
=
1/THROUGHPUT
–5–
TIMING EXAMPLES
Figures 2 and 3 show some of the timing parameters from the
Timing Specifications table.
Timing Example 1
From Figure 3, having f
250 kSPS gives a cycle time of t
With t
satisfies the requirement of 250 ns for t
comprises 2.5(1/f
allows a value of 954 ns for t
quirement of 50 ns.
13
max. This allows a value of 2.19 ms for t
minimum requirement of 50 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary to leave
50 ns minimum t
signal should be fully acquired at approximately point C in
Figure 3.
13
B
B
DB2
2
= 10 ns min, this leaves t
14
14
t
5
C
DB1
15
15
QUIET
SCLK
t
8
DB0
) + t
t
ACQ
between conversions. In this example, the
SCLK
t
16
16
8
8
+ t
= 5 MHz and a throughput rate of
QUIET,
THREE-STATE
QUIET
2
+ 12.5(1/f
ACQ
AD7910/AD7920
satisfying the minimum re-
t
, where t
t
QUIET
QUIET
to be 1.49 ms. This 1.49 ms
ACQ
t
1
QUIET
. From Figure 3, t
SCLK
8
, satisfying the
= 36 ns max. This
) + t
ACQ
= 4 ms.
ACQ