AD7910ARM-REEL AD [Analog Devices], AD7910ARM-REEL Datasheet - Page 4

• Manufacturer Part Number: AD7910ARM-REEL
• Description: 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70
• Manufacturer: AD [Analog Devices]

AD7910/AD7920
AD7920–SPECIFICATIONS
Parameter
POWER REQUIREMENTS
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
Temperature range from –40∞C to +85∞C.
Operational from V
See Terminology section.
B Grade, maximum specs apply as typical figures when V
SC70 values guaranteed by characterization.
Guaranteed by characterization.
See Power vs. Throughput Rate section.
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Minimum f
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V
Measured with a 50 pF load capacitor.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
t
See Power-Up Time section.
8
7
4
4
5
6
V
I
Power Dissipation
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
values apply to t
DD
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Normal Mode (Operational)
Full Power-Down
2
8
SCLK
at which specifications are guaranteed.
8
DD
minimum values also.
= 2.0 V, with input low voltage (V
7
Limit at T
10
5
14
16
50
10
10
22
40
0.4
0.4
10
9.5
7
36
See Note 7
1
AD7910/AD7920
t
t
t
t
SCLK
SCLK
SCLK
SCLK
MIN,
T
1
MAX
1
(V
(continued)
DD
= 2.35 V to 5.25 V, T
A Grade
2.35/5.25
2.5
1.2
3
1.4
1
15
4.2
5
3
INL
DD
) 0.35 V max.
= 4.75 V to 5.25 V.
Unit
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ms max
1, 2
B Grade
2.35/5.25
2.5
1.2
3
1.4
1
15
4.2
5
3
3
A
= T
–4–
MIN
1, 2
to T
Description
AD7910
AD7920
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
V
3.3 V < V
V
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power-Up Time from Full Power-Down
Unit
V min/max
mA typ
mA typ
mA max
mA max
mA max
mW max
mW max
mW max
mW max
MAX
DD
DD
, unless otherwise noted.)
£ 3.3 V
> 3.6 V
DD
8
DD
) and timed from a voltage level of 1.6 V.
, quoted in the Timing Characteristics is the true bus relinquish
£ 3.6 V
Test Conditions/Comments
Digital I/Ps = 0 V or V
V
V
V
V
Typically 50 nA
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
= 4.75 V to 5.25 V, SCLK On or Off
= 2.35 V to 3.6 V, SCLK On or Off
= 4.75 V to 5.25 V, f
= 2.35 V to 3.6 V, f
= 5 V, f
= 3 V, f
= 5 V
= 3 V
DD
= 2.35 V and 0.8 V or 2.0 V for V
SAMPLE
SAMPLE
= 250 kSPS
= 250 kSPS
DD
SAMPLE
SAMPLE
= 250 kSPS
= 250 kSPS
DD
> 2.35 V.
REV. B