CY7C138 CYPRESS [Cypress Semiconductor], CY7C138 Datasheet - Page 10

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CY7C138

Manufacturer Part Number
CY7C138
Description
4K x 8/9 Dual-Port Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Switching Waveforms
Note:
29. If t
CE
CE
Busy Timing Diagram No. 1 (CE Arbitration)
Right Address Valid First:
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
ADDRESS
ADDRESS
L
R
PS
Valid First:
ADDRESS
ADDRESS
Valid First:
ADDRESS
ADDRESS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
BUSY
BUSY
BUSY
BUSY
CE
CE
CE
CE
L,R
L,R
R
R
R
R
L
L
L
L
R
R
L
L
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
t
t
BLA
BLA
[29]
ADDRESS MATCH
ADDRESS MATCH
[29]
t
t
BLC
BLC
10
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C138
CY7C139
C138-19
C138-20
C138-17
C138-18

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