CY7C138 CYPRESS [Cypress Semiconductor], CY7C138 Datasheet - Page 9

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CY7C138

Manufacturer Part Number
CY7C138
Description
4K x 8/9 Dual-Port Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Switching Waveforms
Notes:
26. I/O
27. Semaphores are reset (available to both ports) at cycle start.
28. If t
Timing Diagram of Read with BUSY (M/S=HIGH)
Timing Diagram of Semaphore Contention
Write Timing with Busy Input (M/S=LOW)
ADDRESS
ADDRESS
DATA
DATA IN
SPS
0R
BUSY
A
BUSY
A
R/W
0R
R/W
= I/O
0L
OUTL
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
SEM
SEM
R/W
R/W
–A
–A
0L
R
L
2R
R
R
2L
L
R
R
L
L
= LOW (request semaphore); CE
(continued)
t
PS
R
= CE
t
WB
L
= HIGH
t
MATCH
SPS
MATCH
[26, 27, 28]
t
BLA
[20]
MATCH
MATCH
t
WC
t
PWE
9
t
PWE
t
WH
t
WDD
t
VALID
SD
t
DDD
t
HD
t
BHA
t
BDD
CY7C138
CY7C139
VALID
C138-16
C138-15
C138-14

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