CY7C1360C CYPRESS [Cypress Semiconductor], CY7C1360C Datasheet - Page 7

• Manufacturer Part Number: CY7C1360C
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05540 Rev. *C
Pin Definitions
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQP
V
V
V
V
MODE
TDO
0
DD
SS
SSQ
DDQ
, A
1
2
3
A
C
[2]
, BW
, BW
1
Name
, A
B
D
X
JTAG serial output
Synchronous
I/O Power Supply Power supply for the I/O circuitry.
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Static
I/O-
I/O
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
active. A
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
version. Not connected for BGA. Where referenced, CE
this document for BGA. CE
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized.
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQP
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode pin has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.
1
, A
1
1
1
is sampled only when a new external address is loaded.
PRELIMINARY
0
, A
, A
are fed to the two-bit counter. .
0
0
are also loaded into the burst counter. When ADSP and ADSC are both
are also loaded into the burst counter. When ADSP and ADSC are both
1
1
2
and CE
and CE
and CE
3
2
3
is sampled only when a new external address is loaded.
3
[2]
[2]
to select/deselect the device. Not available for AJ package
to select/deselect the device. CE
to select/deselect the device. ADSP is ignored if CE
Description
X
are placed in a three-state condition.
3
[2]
1
, CE
is assumed active throughout
2
1
, and CE
is deasserted HIGH.
2
is sampled only when
CY7C1360C
CY7C1362C
3
[2]
are sampled
Page 7 of 31
X
and BWE).
1
DD
is