HEF4516B_09 NXP [NXP Semiconductors], HEF4516B_09 Datasheet

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HEF4516B_09

Manufacturer Part Number
HEF4516B_09
Description
Binary up/down counter
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.HEF4516B_09.pdf (16 pages)
1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from
Type number
HEF4516BP
HEF4516BT
Ordering information
Package
Name
DIP16
SO16
−
40
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a
clock input (CP), an up/down count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs
(D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC),
and an overriding asynchronous master reset input (MR).
Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all
other input conditions except for MR which must be LOW. When PL and CE are LOW, the
counter changes on the LOW-to-HIGH transition of CP. Input UP/DN determines the
direction of the count, counting up when HIGH and counting down when LOW. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting
down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter
(Q0 to Q3 = LOW) independent of all other input conditions.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
°
C to +85
HEF4516B
Binary up/down counter
Rev. 06 — 11 December 2009
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
Industrial
Description
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
°
C.
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT109-1
SS

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HEF4516B_09 Summary of contents

Page 1

HEF4516B Binary up/down counter Rev. 06 — 11 December 2009 1. General description The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input ...

Page 2

NXP Semiconductors 5. Functional diagram Fig 1. Functional diagram HEF4516B_6 Product data sheet PARALLEL LOAD CIRCUITRY UP/DOWN UP/DN COUNTER ...

Page 3

NXP Semiconductors UP/DN CE Fig 2. Logic diagram HEF4516B_6 Product data sheet FF1 FF2 ...

Page 4

NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 12, 13 11, 14 ...

Page 5

NXP Semiconductors 7. Functional description [1] Table 3. Function table HIGH voltage level LOW voltage level don’t care; ↑ = positive-going transition. ...

Page 6

NXP Semiconductors Logic equation for terminal count: • ⁄ Fig 5. State diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol ...

Page 7

NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol ...

Page 8

NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t HIGH to LOW PHL propagation delay ...

Page 9

NXP Semiconductors Table 7. Dynamic characteristics ° for test circuit see SS amb Symbol Parameter Conditions t transition time t f maximum frequency see max t pulse width CP input LOW; W ...

Page 10

NXP Semiconductors Table 8. Dynamic power dissipation P P can be calculated from the formulas shown Symbol Parameter dynamic power dissipation 12. Waveforms input V ...

Page 11

NXP Semiconductors negative positive a. Input waveforms b. Test circuit Test data is given in Table 9. Definitions for test circuit: DUT = Device Under Test C = Load capacitance including jig and probe capacitance Termination resistance ...

Page 12

NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. ...

Page 13

NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. ...

Page 14

NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date HEF4516B_6 20091211 • Modifications: Section 9 “Recommended operating conditions” HEF4516B_5 20090812 HEF4516B_4 20090312 HEF4516B_CNV_3 19950101 HEF4516B_CNV_2 19950101 HEF4516B_6 Product data sheet Data sheet status Change notice Product ...

Page 15

NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 16

NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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