MK20DN512VMC10 FREESCALE [Freescale Semiconductor, Inc], MK20DN512VMC10 Datasheet - Page 27

• Manufacturer Part Number: MK20DN512VMC10
• Description: K20 Sub-Family
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
Freescale Semiconductor, Inc.
t
Symbol
fll_acquire
J
J
t
J
f
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
each PCB and results will vary.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
D
pll_ref
cyc_pll
acc_pll
D
cyc_fll
f
I
I
vco
lock
pll
pll
unl
dco_t
) over voltage and temperature should be considered.
FLL period jitter
FLL target frequency acquisition time
VCO operating frequency
PLL operating current
PLL operating current
PLL reference frequency range
PLL period jitter (RMS)
PLL accumulated jitter over 1µs (RMS)
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Description
• f
• f
• PLL @ 96 MHz (f
• PLL @ 48 MHz (f
• f
• f
• f
• f
2 MHz, VDIV multiplier = 48)
2 MHz, VDIV multiplier = 24)
VCO
VCO
vco
vco
vco
vco
= 48 MHz
= 100 MHz
= 48 MHz
= 100 MHz
= 48 MHz
= 98 MHz
Table 15. MCG specifications (continued)
osc_hi_1
osc_hi_1
K20 Sub-Family Data Sheet, Rev. 1, 6/2012.
= 8 MHz, f
= 8 MHz, f
General Business Information
pll_ref
pll_ref
Preliminary
=
=
PLL
± 1.49
± 4.47
48.0
Min.
2.0
—
—
—
—
—
—
—
—
—
—
Peripheral operating requirements and behaviors
1060
1350
Typ.
180
150
600
120
600
50
—
—
—
—
—
—
150 × 10
+ 1075(1/
± 2.98
± 5.97
f
pll_ref
Max.
100
4.0
—
—
—
—
—
—
—
—
1
)
-6
MHz
MHz
Unit
ms
µA
µA
ps
ps
ps
ps
ps
%
%
s
Notes
6
7
7
8
8
9
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