CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 17

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-1. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *B
TQFP
Port A
128
99
35
12
82
83
84
85
89
90
91
11
1
TQFP
100
100
77
10
67
68
69
70
71
72
73
11
QFN
56
42
54
33
34
35
36
37
38
39
5
4
SLOE
PA3 or
WU2
PA4 or
FIFOADR0
PA5 or
FIFOADR1
PA6 or
PKTEND
RESET#
EA
XTALIN
XTALOUT Output
CLKOUT
PA0 or
INT0#
PA1 or
INT1#
PA2 or
Name
Type
Input
Input
Input
O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
[8]
(PA0)
(PA1)
(PA2)
(PA3)
(PA4)
(PA5)
(PA6)
MHz
N/A
N/A
N/A
N/A
12
I
I
I
I
I
I
I
Active LOW Reset. Resets the entire chip. See section 4.9 ”Reset and
Wakeup” on page 5 for more details.
External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches this
code from its internal RAM. IF EA = 1 the 8051 fetches this code from
external memory.
Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square wave
derived from another clock source. When driving from an external source,
the driving signal should be a 3.3V square wave.
Crystal Output. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input
clock. The 8051 defaults to 12-MHz operation. The 8051 may three-state
this output by setting CPUCS.1 = 1.
Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either
edge triggered (IT0 = 1) or level triggered (IT0 = 0).
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either
edge triggered (IT1 = 1) or level triggered (IT1 = 0).
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity (FIFOPIN-
POLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit
(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in
suspend and WU2EN = 1, a transition on this pin starts up the oscillator
and interrupts the 8051 to allow it to exit the suspend mode. Asserting this
pin inhibits the chip from suspending, if WU2EN=1.
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the endpoint
and whose polarity is programmable via FIFOPINPOLAR.5.
Description
CY7C64713/14
Page 17 of 50