CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 34

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

10.5
Table 10-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Table 10-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Notes:
Document #: 38-08039 Rev. *B
17. Dashed lines denote signals with programmable polarity.
18. GPIF asynchronous RDY
19. IFCLK must not exceed 48 MHz.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
Parameter
Parameter
GPIF Synchronous Signals
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
x
signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
X
X
GPIFADR[8:0]
DATA(output)
to Clock Setup Time
to Clock Setup Time
DATA(input)
Figure 10-4. GPIF Synchronous Signals Timing Diagram
RDY
IFCLK
CTL
X
X
X
X
Output Propagation Delay
Output Propagation Delay
X
X
Description
Description
t
SRY
t
SGD
t
XCTL
N
t
XGD
t
IFCLK
valid
t
RYH
t
t
DAH
SGA
N+1
20.83
20.83
Min.
Min.
8.9
9.2
2.9
3.7
3.2
4.5
0
0
[18, 19]
[19]
[17]
Max.
Max.
10.7
11.5
200
7.5
6.7
11
15
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Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns