CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 21

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-1. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *B
TQFP
128
106
101
100
107
32
28
31
30
29
53
52
51
50
42
41
40
38
33
36
37
26
43
48
64
68
81
2
TQFP
100
26
22
84
25
24
23
43
42
41
40
32
31
27
79
29
30
20
33
38
49
53
66
78
85
1
QFN
56
13
14
44
15
16
55
17
27
32
43
11
INT5#
WAKEUP
IFCLK
INT4
T2
T1
T0
RXD1
TXD1
RXD0
TXD0
CS#
WR#
RD#
OE#
Reserved
SCL
SDA
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Name
Type
I/O/Z
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
Output
Output
Input
Input
OD
OD
Power
Power
Power
Power
Power
Power
Power
Power
Power
Default
[8]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
H
H
Z
Z
Z
slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1)
the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5
and IFCONFIG.6. IFCLK may be inverted, whether internally or externally
sourced, by setting the bit IFCONFIG.4 =1.
INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is edge-
sensitive, active HIGH.
INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-
sensitive, active LOW.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the
input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this
pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the input
to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the input
to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit.
RXD1is an active-HIGH input signal for 8051 UART1, which provides data
to the UART in all modes.
TXD1is an active-HIGH output pin from 8051 UART1, which provides the
output clock in sync mode, and the output data in async mode.
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data
to the UART in all modes.
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides
the output clock in sync mode, and the output data in async mode.
CS# is the active-LOW chip select for external memory.
WR# is the active-LOW write strobe output for external memory.
RD# is the active-LOW read strobe output for external memory.
OE# is the active-LOW output enable for external memory.
Reserved. Connect to ground.
USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the
oscillator and interrupts the 8051 to allow it to exit the suspend mode.
Holding WAKEUP asserted inhibits the EZ-USB FX1 chip from suspending.
This pin has programmable polarity (WAKEUP.4).
Clock for the I
I
Data for I
peripheral is attached.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
VCC. Connect to 3.3V power source.
Interface Clock, used for synchronously clocking data into or out of the
2
C peripheral is attached.
2
C interface. Connect to VCC with a 2.2K resistor, even if no I
2
C interface. Connect to VCC with a 2.2K resistor, even if no
Description
CY7C64713/14
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