CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet

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CY7C68000A

Manufacturer Part Number
CY7C68000A
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-08052 Rev. *F
MoBL-USB™ TX2 Features
• Operates in both USB 2.0 high-speed (HS),
• UTMI-compliant/USB 2.0 certified for device operation
• Optimized for seamless interface with Intel
• Tri-state Mode allows sharing of UTMI bus with other
• Serial-to-parallel and parallel-to-serial conversions
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional
• Synchronous field and EOP detection on receive packets
• Synchronous field and EOP generation on transmit packets
• Data and clock recovery from the USB serial stream
• Bit stuffing/unstuffing; bit stuff error detection
• Staging register to manage data rate variation due to bit
• 16-bit 30 MHz and 8-bit 60 MHz parallel interface
• Ability to switch between FS and HS terminations and
• Supports detection of USB reset, suspend, and resume
• Supports HS identification and detection as defined by the
480 Mbits/second, and full-speed (FS), 12 Mbits/second
Applications Processors
devices
external data interface
stuffing/unstuffing
signaling
USB 2.0 Specification
Block Diagram
®
Monahans
198 Champion Court
MoBL-USB™ TX2 USB 2.0 UTMI
The Cypress MoBL-USB™ TX2 is a Universal Serial Bus
(USB) specification revision 2.0 transceiver, serial/deseri-
alizer, to a parallel interface of either 16 bits at 30 MHz or eight
bits at 60 MHz. The MoBL-USB TX2 provides a high-speed
physical layer interface that operates at the maximum
allowable USB 2.0 bandwidth. This allows the system designer
to keep the complex high-speed analog USB components
external to the digital ASIC which decreases development time
and associated risk. A standard interface is provided that is
USB 2.0 certified and is compliant with Transceiver Macrocell
Interface (UTMI) specification version 1.05 dated 3/29/2001.
This product is also optimized to seamlessly interface with
Monahans -P & -L applications processors. It has been
characterized by Intel and is recommended as the USB 2.0
UTMI transceiver of choice for its Monahans processors. It is
also capable of tri-stating the UTMI bus while suspended to
allow the bus to be shared with other devices.
Two packages are defined for the family: 56-pin QFN and
56-pin VFBGA.
The functional block diagram is shown below.
• Supports transmission of resume signaling
• 3.3V operation
• Two package options: 56-pin QFN and 56-pin VFBGA
• All required terminations, including 1.5 Kohm pull up on
• Supports USB 2.0 test modes
DPLUS, are internal to chip
San Jose
,
CA 95134-1709
Revised November 16, 2006
Transceiver
CY7C68000A
Tri_state
408-943-2600

Related parts for CY7C68000A

CY7C68000A Summary of contents

Page 1

... Two packages are defined for the family: 56-pin QFN and 56-pin VFBGA. The functional block diagram is shown below. • 198 Champion Court • San Jose CY7C68000A Transceiver Tri_state , CA 95134-1709 • 408-943-2600 Revised November 16, 2006 ...

Page 2

... Mode 1 allows the transceiver logic to support a soft disconnect feature that tri-states both the HS and FS trans- mitters, and removes any termination from the USB, making it appear to an upstream port that the device has been discon- nected from the bus. CY7C68000A has CC Description Page ...

Page 3

... DPLUS/DMINUS lines and ‘0’s become ‘K’s. DPLUS/DMINUS Impedance Termination The CY7C68000A does not require external resistors for USB data line impedance termination or an external pull up resistor Pin Assignments The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages. ...

Page 4

... Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment CY7C68000A Pin Descriptions [1] Table 1. Pin Descriptions QFN VFBGA Name Type 4 H1 AVCC Power 8 H5 AVCC Power 7 H4 AGND Power 11 H8 AGND Power 9 H6 DPLUS I/O DMINUS I/O/Z Note 1 ...

Page 5

... HS termination 1: FS termination N/A Suspend Places the CY7C68000A in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operations. While suspended, TermSelect must always mode to ensure that the 1.5 Kohm pull up on DPLUS remains powered. ...

Page 6

... TX Holding Register on the rising edge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000A will load the data on the data bus into the TX Holding Register on the next rising edge of CLK. At that time, the SIE ...

Page 7

... Uni_Bidi is static after power-on reset (POR Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source. CC N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. CY7C68000A Description Page ...

Page 8

... Crystal Frequency) ... 24 MHz ± 100 ppm OSC ................................................................... Parallel Resonant + 0.5V CC Conditions 0< V < OUT I = –4 mA OUT Except DPLUS/DMINUS/CLK DPLUS/DMINUS/CLK Output pins [2] Connected [2] Disconnected Normal operation OPMOD[1: Normal operation OPMOD[1: CY7C68000A Min. Typ. Max. Unit 3.0 3.3 3 5.25 V –0.5 0.8 V µA ±10 2 ...

Page 9

... Clock to Control out time for TXReady, RXValid, CCO RXActive and RXError T Clock to Data out time (Receive direction) CDO Document #: 38-08052 Rev. *F Figure 3. 60-MHz Interface Timing Constraints TCH_MIN TDH_MIN TCCO TCDO Description Min. CY7C68000A Typ. Max. Unit ...

Page 10

... Minimum set-up time for Tri-state tssu T Propagation Delay for Tri-State mode tspd Document #: 38-08052 Rev. *F TCH_MIN TDH_MIN TCDO TCCO TCVO TVH_MIN Description Min. Figure 5. Tri-state Mode Timing Constraints Ttssu Ttspd XXXX Hi-Z Description Min. CY7C68000A Typ. Max. Unit ...

Page 11

... Document #: 38-08052 Rev. *F Package Type 56 QFN 56 VFBGA MoBL-USB TX2 Development Board SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.20[0.008] REF. 0.04[0.0015] MAX. 0.30[0.012] 0.50[0.020] C SEATING PLANE CY7C68000A BOTTOM VIEW PIN #1 0.18[0.007] 0.28[0.011] CORNER E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.50[0.020] 6.45[0.254] 6.55[0.258] 51-85187-*A Page ...

Page 12

... Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the CY7C68000A BOTTOM VIEW Ø0. Ø0. CORNER Ø0.30±0.05(56X) ...

Page 13

... Figure plot of the solder mask pattern image of the assembly (darker areas indicate solder). 0.017” dia Solder Mask Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane CY7C68000A Page ...

Page 14

... Document History Page Document Title: CY7C68000A MoBL-USB™ TX2 USB 2.0 UTMI Transceiver Document Number: 38-08052 REV. ECN NO. Issue Date ** 285592 See ECN *A 427959 See ECN *B 470121 See ECN *C 476107 See ECN *D 491668 See ECN *E 498415 See ECN *F 567869 See ECN Document #: 38-08052 Rev. *F Orig ...

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