CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet - Page 3

• Manufacturer Part Number: CY7C68000A
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08052 Rev. *F
Mode 2 disables Bit Stuff and NRZI encoding logic so ‘1’s
loaded
DPLUS/DMINUS lines and ‘0’s become ‘K’s.
DPLUS/DMINUS Impedance Termination
The CY7C68000A does not require external resistors for USB
data line impedance termination or an external pull up resistor
Pin Assignments
The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages.
The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface.
from
TermSelect
XcvrSelect
XTALOUT
OpMode0
TXReady
Suspend
DMINUS
XTALIN
DPLUS
AGND
AGND
Reset
AV
AV
the
CC
CC
data
10
11
12
13
14
1
2
3
4
5
6
7
8
9
bus
becomes
Figure 1. CY7C68000A 56-pin QFN Pin Assignment
‘J’s
on
CY7C68000A
56-pin QFN
56-pin QFN
the
on the DPLUS line. These resistors are incorporated into the
part. They are factory trimmed to meet the requirements of
USB 2.0. Incorporating these resistors also reduces the pin
count on the part.
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
D5
Reserved
D6
D7
D8
D9
Reserved
D10
D11
V
D12
GND
D13
CC
CY7C68000A
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