CY7C68000A CYPRESS [Cypress Semiconductor], CY7C68000A Datasheet - Page 2

• Manufacturer Part Number: CY7C68000A
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08052 Rev. *F
Applications
Mobile Applications
Consumer Applications
Non-Consumer Applications
Functional Overview
The functionality of this chip is described in the sections below.
USB Signaling Speed
The MoBL-USB TX2 operates at two of the rates defined in the
USB Specification 2.0, dated April 27, 2000.
The MoBL-USB TX2 does not support the low-speed (LS)
signaling rate of 1.5 Mbps.
Transceiver Clock Frequency
The MoBL-USB TX2 has an on-chip oscillator circuit that uses
an external 24 MHz (±100-ppm) crystal with the following
characteristics:
An on-chip phase-locked loop (PLL) multiplies the 24 MHz
oscillator up to 30/60 MHz, as required by the transceiver
parallel data bus. The default UTMI interface clock (CLK)
frequency is determined by the DataBus16_8 pin.
Buses
The two packages allow for a 8- or 16-bit bidirectional data bus
for data transfers to a controlling unit.
Suspend and Tri-state Modes
When the MoBL-USB TX2 is not in use, the processor can
reduce power consumption by putting it into Suspend mode
using the Suspend pin.
While in Suspend mode, Tri-state mode may be enabled,
which tri-states all outputs and IO’s, allowing the UTMI
• Smart Phones
• PDA Phones
• Gaming Phones
• MP3 players
• Portable Media Players (PMP)
• GPS Tracking Devices
• Cameras
• Scanners
• DSL Modems
• Memory Card Readers
• Networking
• Wireless LAN
• Home PNA
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps
• Parallel resonant
• Fundamental mode
• 500 µW drive level
• 27–33 pF (5% tolerance) load capacitors
interface pins to be shared with other devices. This is valuable
in mobile handset applications, where GPIO’s are at a
premium. The outputs and IO’s will be tri-stated ~50ns
following Tri-state Mode being enabled, and will be driven
~50ns following Tri-state Mode being disabled. All inputs must
not be left floating while in Tri-state Mode.
When resuming after a suspend, the PLL stabilizes approxi-
mately 200 µs after the suspend pin goes high.
Reset Pin
An input pin (Reset) resets the chip. This pin has hysteresis
and is active HIGH according to the UTMI specification. The
internal PLL stabilizes approximately 200 µs after V
reached 3.3 volts.
Line State
The Line State output pins LineState[1:0] are driven by combi-
national logic and may be toggling between the ‘J’ and the ‘K’
states. They are synchronized to the CLK signal for a valid
signal. On the CLK edge the state of these lines reflect the
state of the USB data lines. Upon the clock edge the ‘0’ bit of
the LineState pins is the state of the DPLUS line and the ‘1’ bit
of LineState is the DMINUS line. When synchronized, the set-
up and hold timing of the LineState is identical to the parallel
data bus.
Full-speed vs. High-speed Select
The FS vs. HS is done through the use of both XcvrSelect and
the TermSelect input signals. The TermSelect signal enables
the 1.5 Kohm pull up on to the DPLUS pin. When TermSelect
is driven LOW, a SE0 is asserted on the USB providing the HS
termination and generating the HS Idle state on the bus. The
XcvrSelect signal is the control that selects either the FS trans-
ceivers or the HS transceivers. By setting this pin to a’0’ the
HS transceivers are selected and by setting this bit to a’1’ the
FS transceivers are selected.
Operational Modes
The operational modes are controlled by the OpMode signals.
The OpMode signals are capable of inhibiting normal
operation of the transceiver and evoking special test modes.
These modes take effect immediately and take precedence
over any pending data operations. The transmission data rate
when in OpMode depends on the state of the XcvrSelect
input.
Mode 0 allows the transceiver to operate with normal USB
data decoding and encoding.
Mode 1 allows the transceiver logic to support a soft
disconnect feature that tri-states both the HS and FS trans-
mitters, and removes any termination from the USB, making it
appear to an upstream port that the device has been discon-
nected from the bus.
OpMode[1:0]
00
01
10
11
Mode
0
1
2
3
Normal operation
Non-driving
Disable Bit Stuffing and NRZI
encoding
Reserved
CY7C68000A
Description
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