CY7C68300 CYPRESS [Cypress Semiconductor], CY7C68300 Datasheet - Page 10

• Manufacturer Part Number: CY7C68300
• Manufacturer: CYPRESS [Cypress Semiconductor]

2.3.4
ATA_EN allows bus sharing with other host devices. Setting ATA_EN = 1 enables the ATA interface for normal operation. Setting
ATA_EN = 0 disables (High-Z) the ATA interface pins and removes the EZ-USB AT2 from the USB. The ATA_EN pin is sampled
at a rate of 60 times per second by the EZ-USB AT2 internal logic. This pin should be set to a HIGH at start-up. Upon a HIGH to
LOW transition all EZ-USB AT2 ATA signals are tri-stated, USB is disconnected, and the EZ-USB AT2 enters an idle state until
an active Reset is received, or the ATA_EN pin transitions back to a HIGH state. Upon sensing the LOW to HIGH transition the
EZ-USB AT2 will return to the post Reset operational state, and will reconnect to USB. Note that disabling the ATA bus with the
ATA_EN pin during the middle of a data transfer will result in data loss and can cause the operating system on the Host computer
to crash.
2.3.5
Design practices as outlined in the ATA/ATAPI-6 Specification for signal integrity should be followed with systems that utilize
a ribbon cable interconnect between the EZ-USB AT2’s ATA interface and the attached ATA/ATAPI device, especially if Ultra DMA
Mode is utilized.
2.3.6
VBUS_PWR_VALID indicates to the EZ-USB AT2 that power is present on VBUS.
2.3.7
Asserting RESET# for 10 ms will reset the entire chip. This pin is normally tied to V
a 0.1- F capacitor.
3.0
The EZ-USB AT2 is a high-speed USB 2.0 peripheral device that connects ATA or ATAPI storage devices to a USB host using
the USB Mass Storage Class protocol.
3.1
Document #: 38-08011 Rev. *B
• CY4615 EZ-USB AT2 Reference Design Kit
• USB Specification version 2.0
• ATA Specification T13/1410D Rev 3B
• USB Mass Storage Class Bulk Only Transport Specification, http://www.usb.org/developers/data/devclass/
usbmassbulk_10.pdf.
ATA_EN
ATA Interface Pins
VBUS_PWR_VALID
RESET#
Additional Resources
Applications
2 0 p F
Figure 2-3. XTALIN, XTALOUT Diagram
Figure 2-4. Typical Reset Circuit
2 4 M H z crys ta l
N R E S E T
1 0 0 K
0 . 1
R 8
C 1
u F d
CC
through a 100k resistor, and to GND through
2 0 p F
CY7C68300
Page 10 of 26