CY7C68300 CYPRESS [Cypress Semiconductor], CY7C68300 Datasheet - Page 9

• Manufacturer Part Number: CY7C68300
• Manufacturer: CYPRESS [Cypress Semiconductor]

2.2
2.3
2.3.1
DPLUS and DMINUS are the USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB.
2.3.2
The clock and data pins for the I
resistors.
2.3.3
The EZ-USB AT2 requires a 24-MHz signal to derive internal timing. Typically a 24-MHz parallel-resonant fundamental mode
crystal is used, but a 24-MHz square wave from another source can also be used. If a crystal is used, connect the pins to XTALIN
and XTALOUT, and also through 20-pF capacitors to GND. If an alternate clock source is used, apply it to XTALIN and leave
XTALOUT open.
Note:
Document #: 38-08011 Rev. *B
2.
SSOP
Pin
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
A # sign after the signal name indicates it is an active LOW signal.
QFN
Pin Descriptions
Additional Pin Descriptions
DPLUS, DMINUS
SCL, SDA
XTALIN, XTALOUT
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VBUS_PW
Pin Name
ARESET#
DIOW#
DMACK#
R_VALID
RESET#
ATA_EN
INTRQ
DIOR#
CS0#
CS1#
DD10
DD11
DD12
GND
DD8
DD9
V
DA0
DA1
DA2
V
CC
CC
[2]
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
PWR
PWR
Type
GND
I/O
I/O
I/O
I/O
I/O
Pin
I
(continued)
[1]
I
I
I
2
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
C-compatible port should be connected to your configuration EEPROM and to V
Driven high after 2 ms delay
Driven high after 2 ms delay
Driven high after 2 ms delay
Driven high after 2 ms delay
Driven high after 2 ms delay
Input – If AT2 is not in mfg
mode, polled every 20 ms after
start-up. If LOW, SSOP: pins
36–38, 41–45 and 47 are
three-stated. QFN: pins
29–31, 34–38 and 40 are
three-stated.
Default State at Start-up
Driven high (CMOS)
Driven high (CMOS)
Driven high (CMOS)
Input
Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ATA Control.
ATA Control.
ATA Control.
V
IDE ATA Interrupt request.
ATA Address.
ATA Address.
ATA Address.
ATA Chip Select.
ATA Chip Select.
VBUS detection. Indicates to the EZ-USB AT2 that VBUS
power is present.
ATA Reset.
Ground.
Active LOW Reset. Resets the entire chip. This pin is
normally tied to VCC through a 100K resistor, and to GND
through a 0.1-µF capacitor, supplying a 10-ms reset.
V
Active HIGH. ATA interface enable. Allows ATA bus sharing
with other host devices. Setting ATA_EN=1 enables the ATA
interface for normal operation. Disabling ATA_EN three-
states (High-Z) the ATA interface and halts the ATA interface
state machine logic.
ATA Data bit 8.
ATA Data bit 9.
ATA Data bit 10.
ATA Data bit 11.
ATA Data bit 12.
CC
CC
. Connect to 3.3V power source.
. Connect to 3.3V power source.
Pin Description
CY7C68300
CC
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