AD2S93BP AD [Analog Devices], AD2S93BP Datasheet - Page 3

• Manufacturer Part Number: AD2S93BP
• Description: Low Cost LVDT-to-Digital Converter
• Manufacturer: AD [Analog Devices]

Parameter
SERIAL CLOCK (SCLK)
POWER SUPPLY
NOTES
1
2
3
4
Specifications subject to change without notice.
Parameter
t
t
t
t
t
t
t
NOTE
1
REV. A
The signal input voltage maximum should always be set at 10% less than the reference input.
Nominal + FS = V
With G = 10; Sensitivity 34.2 V pk/LSB
Phase shift cause gain errors. “See Phase Shift and Quadrative Effects.”
SCLK can only be applied after t
1
2
3
4
5
6
7
TIMING CHARACTERISTICS
1
SCK Input Rate
Maximum Read Rate (16 Bits)
I
I
DD
SS
A–B
= V
REF
/2, FS = –V
2
has elapsed.
AD2S93
150
600
250
250
100
600
150
SCLK
DATA
CS
A–B
= V
t
1
REF
t * = THE MINIMUM ACCESS TIME: USER DEPENDENT
TOTAL MAX READ TIME =
TOTAL MAX READ TIME = 600 +16 (250 + 250) + 150 ns
TOTAL MAX READ TIME = 600 + 8000 + 150 ns
TOTAL MAX READ TIME = 8.750 µs (SINGLE READ ONLY)
/2
(V
DD
t
2
= +5 V
Test Conditions
Continuous
Units
ns max
ns min
ns min
ns min
ns max
ns min
ns max
t
3
5%, AGND = DGND = 0 V, T
Timing Diagram
t
MSB
2
+ 16. (
t
t
5
4
t
–3–
3
+
t
4
) +
t
7
A
= –40 C to +85 C unless otherwise noted)
Min
5
5
t
7
Test Conditions
CS to DATA Enable
CS to 1st SCLK Positive Edge
SCLK High Pulse
SCLK Low Pulse
SCLK Positive Edge to DATA Valid
CS High Pulse Width
CS High to DATA High Z (Bus Relinquish)
t
LSB
*
Typ
7
7
t
6
Max
2
9.2
10
10
AD2S93
Units
MHz
mA
mA
s