PCF2114AU/10 PHILIPS [NXP Semiconductors], PCF2114AU/10 Datasheet - Page 28

• Manufacturer Part Number: PCF2114AU/10
• Description: LCD controller/drivers
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
11 INTERFACE TO MICROCONTROLLER
11.1
The I
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.
11.2
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
11.3
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
11.4
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
1997 Apr 07
LCD controller/drivers
(I
2
2
C-bus is for bidirectional, two-line communication
C-BUS INTERFACE)
Characteristics of the I
Bit transfer
START and STOP conditions
System configuration
2
C-bus
28
11.5
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
11.6
Before any data is transmitted on the I
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I
PCF2116 READ and WRITE cycles is shown in
Figs 25 to 27.
Acknowledge
I
2
C-bus protocol
2
C-bus configuration for the different
PCF2116 family
Product specification
2
C-bus, the device