PCF85116-3P/01 PHILIPS [NXP Semiconductors], PCF85116-3P/01 Datasheet - Page 12

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PCF85116-3P/01

Manufacturer Part Number
PCF85116-3P/01
Description
2048 x 8-bit CMOS EEPROM with I2C-bus interface
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
Philips Semiconductors
11. I
Table 8:
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
with an input voltage swing from V
[1]
[2]
9397 750 14217
Product data
Symbol
f
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
f
SU;STO
Fig 9. Timing requirements for the I
SCL
SDA
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
C
b
P = STOP condition; S = START condition.
2
= total capacitance of one bus line in pF.
C-bus characteristics
I
P
Parameter
clock frequency
time the bus must be free before
new transmission can start
START condition hold time after
which first clock pulse is generated
LOW level clock period
HIGH level clock period
set-up time for START condition
data hold time
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
2
C-bus characteristics
for CBUS compatible masters
for I
t BUF
2
C-bus devices
S
t
HD;STA
t LOW
SS
t r
to V
2
DD
C-bus.
; see
t
HD;DAT
Figure
Rev. 04 — 25 October 2004
Conditions
repeated start
t HIGH
9.
t f
t
SU;DAT
2048
[1]
Standard mode
Min
0
4.7
4.0
4.7
4.0
4.7
5
0
250
-
-
4.0
8-bit CMOS EEPROM with I
t
SU;STA
Max
100
-
-
-
-
-
-
-
-
1000
300
-
S
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
t
HD;STA
Fast mode
Min
0
1.3
0.6
1.3
0.6
0.6
-
0
100
20 + 0.1C
20 + 0.1C
0.6
PCF85116-3
MBA705
b
b
[2]
[2]
2
C-bus interface
Max
400
-
-
-
-
-
-
-
-
300
300
-
t
SU;STO
IL
and V
P
12 of 21
Unit
kHz
ns
ns
ns
s
s
s
s
s
s
s
s
IH

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