PCF2127AT/1 NXP [NXP Semiconductors], PCF2127AT/1 Datasheet - Page 49
PCF2127AT/1
Manufacturer Part Number
PCF2127AT/1
Description
Integrated RTC, TCXO and quartz crystal
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF2127AT1.pdf
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NXP Semiconductors
PCF2127A_2
Product data sheet
8.13.4 Watchdog timer interrupts
8.13.5 Alarm interrupts
The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0]
bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which
follows the status of the watchdog timer flag WDTF (register Control_2). No pulse
generation is possible for watchdog timer interrupts.
The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot
be cleared by using the interface. Instructions for clearing it can be found in
Section
Generation of interrupts from the alarm function is controlled via the bit AIE (register
Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register
Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for
alarm interrupts.
Fig 29. Example of shortening the INT pulse by clearing the CDTF flag
Fig 30. AF timing diagram
(1) Indicates normal duration of INT pulse.
8.11.6.
The timing shown for clearing CDTF is also valid for the non-pulsed interrupt mode, i.e. when
TI_TP is logic 0, where the INT pulse may be shortened by setting CDTIE logic 0.
Example where only the minute alarm is used and no other interrupts are enabled.
countdown counter
minute counter
All information provided in this document is subject to legal disclaimers.
minute alarm
instruction
instruction
SCL
CDTF
INT
AF
SCL
INT
Rev. 02 — 7 May 2010
44
45
01
45
n
CLEAR INSTRUCTION
CLEAR INSTRUCTION
Integrated RTC, TCXO and quartz crystal
8th clock
8th clock
PCF2127A
001aaf910
001aaf909
© NXP B.V. 2010. All rights reserved.
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