PCF85133U/2DA/1 NXP [NXP Semiconductors], PCF85133U/2DA/1 Datasheet
PCF85133U/2DA/1
Related parts for PCF85133U/2DA/1
PCF85133U/2DA/1 Summary of contents
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PCF85133 Universal LCD driver for low multiplex rates Rev. 1 — 17 February 2009 1. General description The PCF85133 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name PCF85133U/2DA/1 PCF85133 [1] Bump hardness see Table 20. 4. Marking Table 2. Type number PCF85133U/2DA/1 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR FF SCL INPUT FILTERS SDA Fig 1 ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Top view. For mechanical details, see Fig 2. Pinning of PCF85133 6.2 Pin description Table 3. Symbol SDAACK SDA SCL CLK V DD SYNC OSC FF A0, A1 and A2 SA0 V SS ...
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NXP Semiconductors 7. Functional description The PCF85133 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes ...
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NXP Semiconductors 7.1 Power-on reset At power-on the PCF85133 resets to the following starting conditions: • All backplane and segment outputs are set to V • The selected drive mode is 1:4 multiplex with • Blinking is switched off • ...
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NXP Semiconductors The RMS on-state voltage ( RMS where for static mode for 1:2 multiplex for 1:3 multiplex for 1:4 multiplex The RMS off-state voltage ...
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NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig 4. ...
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NXP Semiconductors 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85133 allows the use of Figure 6. Fig 5. PCF85133_1 Product data sheet 1 1 bias ...
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NXP Semiconductors Fig 6. PCF85133_1 Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD ...
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NXP Semiconductors 7.4.3 1:3 multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Fig 7. PCF85133_1 Product data sheet Figure 7. V LCD LCD BP0 V ...
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NXP Semiconductors 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 8. PCF85133_1 Product ...
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NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85133 are timed by a frequency f which either is derived from the built-in oscillator frequency clk or equals an external clock frequency ...
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NXP Semiconductors 7.8 Segment outputs The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data ...
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NXP Semiconductors • In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1 and 2 of three successive 4-bit RAM words, with bit 3 of the third address left unchanged not recommended to ...
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LCD segments LCD backplanes S a n+2 b BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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NXP Semiconductors 7.12 Subaddress counter The storage of display data is conditioned by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0, A1 and ...
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NXP Semiconductors Table 7. Blink mode off additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication ...
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NXP Semiconductors 7.16.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time ...
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NXP Semiconductors 7.16.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level ...
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NXP Semiconductors 7.16.5 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 2 7.16.6 I C-bus protocol 2 Two I C-bus slave addresses (0111 000 and 0111 001) ...
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NXP Semiconductors R slave address control byte EXAMPLES a) transmit two bytes of RAM data ...
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NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCF85133 are defined in Table 9. Command mode-set load-data-pointer device-select bank-select blink-select Table 10. Bit ...
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NXP Semiconductors Table 13. See Section Bit [1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. Table 14. See Section Bit [1] Normal ...
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NXP Semiconductors 8. Internal circuitry SA0, CLK, SYNC, OSC, Fig 17. Device protection diagram PCF85133_1 Product data sheet V DD FF, A0, A1 LCD BP0, BP1, BP2, BP3 S79 V SS Rev. 1 — ...
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NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 15. In accordance with the Absolute Maximum Rating System ...
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NXP Semiconductors 10. Static characteristics Table 16. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD V power-on reset voltage POR ...
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NXP Semiconductors 11. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter Clock Internal: output pin CLK f clock frequency clk f frame frequency fr External: input ...
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NXP Semiconductors BP0 to BP3, and S0 to S79 Fig 18. Driver timing waveforms SDA SCL SDA Fig 19. I PCF85133_1 Product data sheet CLK t clk(H) CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv ...
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NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations sixteen PCF85133s can be recognized on the 2 same I programmable I Table 18. Cluster 1 2 When cascaded PCF85133s are synchronized, they can share ...
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NXP Semiconductors SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF85133 asserts the SYNC line at the onset of its last active backplane signal and monitors ...
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NXP Semiconductors Fig 21. Synchronization of the cascade for the various PCF85133 drive modes PCF85133_1 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) ...
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... NXP Semiconductors 13. Bare die description 13.1 General description Table 20. Type number PCF85133U/2DA/1 [1] Pressure of diamond head 13.2 Alignment marks Fig 22. Alignment marks of PCF85133 Table 21. Symbol S1 C1 13.3 Bump locations Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip ...
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NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol SYNC OSC ...
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NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 ...
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NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each bump with respect to the center (x the chip; see Symbol S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 ...
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NXP Semiconductors 14. Bare die outline Bare die; 110 bumps; 4.16 x 1. 110 1 e Dimensions (1) (1) (1) Unit max 0.018 mm nom 0.380 0.015 0.0338 4.156 1.069 0.054 ...
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NXP Semiconductors 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A , IEC 61340-5 or ...
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NXP Semiconductors Fig 25. Tray alignment for PCF85133 tray Table 23. See Figure Symbol The orientation of the pocket is indicated by the position of the IC type name ...
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NXP Semiconductors 17. Abbreviations Table 24. Acronym CMOS COG DC HBM ITO LCD MM RAM RC RMS 18. Revision history Table 25. Revision history Document ID Release date PCF85133_1 20090217 PCF85133_1 Product data sheet Abbreviations Description ...
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NXP Semiconductors 19. Legal information 19.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...