PCF85134HL-1 NXP [NXP Semiconductors], PCF85134HL-1 Datasheet - Page 32

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PCF85134HL-1

Manufacturer Part Number
PCF85134HL-1
Description
Universal LCD driver for low multiplex rates
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PCF85134_1
Product data sheet
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85134. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex drive mode when PCF85134
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF85134 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF85134 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF85134 are shown in
Fig 20. Cascaded PCF85134 configuration
V
V
V
DD
CONTROLLER
SS
PROCESSOR/
LCD
MICRO-
MICRO-
HOST
R
2C
t
r
b
Rev. 01 — 17 December 2009
SYNC
SYNC
OSC
SDA
SCL
CLK
OSC
SDA
CLK
SCL
A0
Universal LCD driver for low multiplex rates
A0
A1
PCF85134
PCF85134
V DD
A1
V
DD
A2
A2 SA0
V LCD
SA0
V
LCD
V
SS
V
Figure
SS
60 segment drives
60 segment drives
4 backplanes
BP0 to BP3
BP0 to BP3
(open-circuit)
21.
PCF85134
© NXP B.V. 2009. All rights reserved.
LCD PANEL
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