PCF8531U NXP [NXP Semiconductors], PCF8531U Datasheet - Page 13

• Manufacturer Part Number: PCF8531U
• Description: 34 x 128 pixel matrix driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
7. Functional description
PCF8531_4
Product data sheet
7.10 Bias voltage generator
7.1 Oscillator
7.2 Power-on reset
7.3 I
7.4 Input filters
7.5 Display data RAM
7.6 Timing generator
7.7 Address counter
7.8 Display address counter
7.9 Command decoder
The on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC input must be connected to V
signal, if used, is connected to this input.
The on-chip power-on reset initializes the chip after power-on or power failure.
The I
I
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
The PCF8531 contains 34
The RAM is divided into 6 banks of 128 bytes (6
data. During RAM access, data is transferred to the RAM via the I
is a direct correspondence between the X address and column output number.
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not affected by operations on the data buses.
The address counter sets the addresses of the display data RAM for writing.
The display address counter generates the addresses for read out of the display data.
The command decoder identifies command words that arrive on the I
determines the destination for the following data bytes.
The bias voltage generator generates four buffered intermediate bias voltages. This block
contains the generator for the reference voltages and the four buffers. This block can
operate in two voltage ranges:
2
2
C-bus slave receiver and therefore it cannot control bus communication.
•
C-bus controller
Normal mode: 4.0 V to 9.0 V
2
C-bus controller receives and executes the commands. The PCF8531 acts as an
Rev. 04 — 13 June 2008
128 bits static RAM for storing the display data, see
8
128 bits). Bank 5 is used for icon
34 x 128 pixel matrix driver
2
C-bus interface. There
DD
2
C-bus and
PCF8531
. An external clock
© NXP B.V. 2008. All rights reserved.
Figure
13 of 44
7.