PCF8563BS NXP [NXP Semiconductors], PCF8563BS Datasheet - Page 6

no-image

PCF8563BS

Manufacturer Part Number
PCF8563BS
Description
Real-time clock/calendar
Manufacturer
NXP [NXP Semiconductors]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8563BS/4
Manufacturer:
NXP
Quantity:
2 000
Part Number:
PCF8563BS/4,118
Manufacturer:
NXP
Quantity:
143
Part Number:
PCF8563BS/4118
Manufacturer:
NXP Semiconductors
Quantity:
55 483
Part Number:
PCF8563BS/4Ј¬118
Manufacturer:
NXP
Quantity:
50
NXP Semiconductors
Table 3.
Bit positions labelled as x are not relevant. Bit positions labelled with 0 should always be written with logic 0; if read they could
be either logic 0 or logic 1.
PCF8563_6
Product data sheet
Address Register name
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
control_status_1
control_status_2
VL_seconds
minutes
hours
days
weekdays
century_months
years
minute_alarm
hour_alarm
day_alarm
weekday_alarm
CLKOUT_control
timer_control
timer
Formatted registers overview
7.6.1 Control_status_1 register
7.6.2 Control_status_2 register
7.6 Register organization
Table 4.
Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer
countdown, TF is set to logic 1. These bits maintain their value until overwritten by
software. If both timer and alarm interrupts are required in the application, the source of
the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another a logic AND is performed during a write access.
Bit
7
6
5
4
3
2 to 0
TEST1
Bit 7
AE
AE
AE
AE
VL
FE
TE
Symbol
TEST1
0
STOP
0
TESTC
0
C
0
x
x
x
x
Control_status_1 - Control and Status register 1 (address 00h) bit description
Bit 6
Value
0
1
0
1
0
1
0
0
x
x
x
x
x
x
x
x
x
Rev. 06 — 21 February 2008
Description
Normal mode
EXT_CLK test mode
default value is logic 0
RTC source clock runs
all RTC divider chain flip-flops are asynchronously set to logic 0; the
RTC clock is stopped (CLKOUT at 32.768 kHz is still available)
default value is logic 0
Power-on reset override facility is disabled; set to logic 0 for normal
operation
Power-on reset override may be enabled
default value is logic 0
STOP
Bit 5
0
x
x
x
x
x
<years 00 to 99 coded in BCD>
<minute alarm 00 to 59 coded in BCD>
<timer countdown value>
<seconds 00 to 59 coded in BCD>
<minutes 00 to 59 coded in BCD>
TI_TP
Bit 4
<hour alarm 00 to 23 coded in BCD>
0
x
<day alarm 01 to 31 coded in BCD>
x
x
x
<hours 00 to 23 coded in BCD>
<days 01 to 31 coded in BCD>
<months 01 to 12 coded in BCD>
TESTC
Bit 3
AF
x
x
x
x
<weekday alarm 0 to 6 in BCD>
Bit 2
<weekdays 0 to 6 in BCD>
TF
0
x
x
Real-time clock/calendar
PCF8563
© NXP B.V. 2008. All rights reserved.
Bit 1
FD1
TD1
AIE
0
Bit 0
FD0
TD0
TIE
0
6 of 32

Related parts for PCF8563BS