PCA85232DA NXP [NXP Semiconductors], PCA85232DA Datasheet - Page 21

• Manufacturer Part Number: PCA85232DA
• Description: LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA85232
Product data sheet
7.14 Input bank selector
7.15 Blinker
7.16 Characteristics of the I
The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table
The display blinking capabilities of the PCA85232 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see
frequencies are fractions of the clock frequency. The ratios between the clock and blink
frequencies depend on the blink mode in which the device is operating (see
Table 6.
Assuming that f
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command (see
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD elements can blink selectively by changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blinking frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see
The I
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
Blink mode
off
1
2
3
2
14). The input bank selector functions independently to the output bank selector.
C-bus is for bidirectional, two-line communication between different ICs or modules.
Blink frequencies
clk
All information provided in this document is subject to legal disclaimers.
= 3.500 kHz.
Rev. 1 — 8 December 2010
Operating mode ratio
-
f
f
blink
f
blink
blink
2
C-bus
=
=
=
----------- -
3072
----------- -
1536
f
-------- -
768
f
f
clk
clk
clk
Table
Table
LCD driver for low multiplex rates
10).
Blink frequency
blinking off
~4.56 Hz
~2.28 Hz
~1.14 Hz
15).
PCA85232
Table
© NXP B.V. 2010. All rights reserved.
15). The blink
Table
6).
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