M41T00AUDD1E STMICROELECTRONICS [STMicroelectronics], M41T00AUDD1E Datasheet
M41T00AUDD1E
Available stocks
Related parts for M41T00AUDD1E
M41T00AUDD1E Summary of contents
Page 1
Features ■ Combination real-time clock with audio – Serial RTC based on M41T00 – Audio section provides: – 300mW differential audio amplifier – 256 and 512Hz tone generation – -33 to +12dB gain, 3dB steps (16 steps plus MUTE) ■ ...
Page 2
Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
Initial conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Description The M41T00AUD is a low power serial real-time clock (RTC) with an integral audio section with tone generator and 300mW output amplifier. The RTC is a superset of the M41T00 with enhancements such as a precision reference for ...
Page 7
Pin settings 2.1 Pin connection Figure 2. Pin connection 2.2 Pin description Table 1. Pin description Symbol V CC OSCI OSCO SCL SDA AIN V BIAS V SS AOUT– AOUT+ IRQ/FT/OUT V BACK FBK NC No name; exposed pad ...
Page 8
Application Figure 3. Application diagram 8/44 M41T00AUD V CC AUTOMATIC BATTERY V INT SWITCHOVER & DESELEC T REFERENCE V PFD =2.80V WRITE (SDA, PROTECT SCL 400kHz I 2 ...
Page 9
Figure 4. Typical hookup example 3.3V SCL SDA 32.768kHz R2 should be a minimum of 10kΩ Audio R1 20kΩ In Set R1’ for unity gain R1 x 20kΩ 20kΩ Optional: can sum additional audio inputs ...
Page 10
Operation The M41T00AUD clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 10 bytes contained in the device can then be accessed ...
Page 11
This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected ...
Page 12
Figure 5. Serial bus data transfer sequence CLOCK DATA START CONDITION Figure 6. Acknowledgement sequence SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Figure 7. Bus timing requirements sequence SDA tBUF SCL STOP ...
Page 13
Characteristics Table 3. AC characteristics Symbol f SCL clock frequency SCL t Clock Low period LOW t Clock High period HIGH t SDA and SCL Rise time R t SDA and SCL Fall time F START condition Hold time ...
Page 14
Figure 8. Slave address location START Figure 9. READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 10. Alternate READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS 14/44 ...
Page 15
WRITE mode In this mode the master transmitter transmits to the M41T00AUD slave receiver. Bus protocol is shown in (R placed on the bus and indicates to the addressed device that word address An will follow ...
Page 16
M41T00AUD clock operation 5.1 Clock registers The 10-byte Register Map (see and time from the clock binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three registers. Bits register ...
Page 17
Register 08 is the calibration register. Calibration is described in detail in the Clock calibration section. Bit D7 is the OUT bit and controls the discrete output pin IRQ/FT/OUT as described in Table 5.1.1 Halt bit operation Bit D7 of ...
Page 18
Reading and writing the clock registers The counters used to implement the timing chain in the real-time clock are not directly accessed by the serial interface. Instead, as depicted in buffered through a set of transfer registers. This ensures ...
Page 19
Table 4. M41T00AUD register map Addr 00h ST 10 seconds (2) 0 01h 10 minutes 02h CEB CB 10 hours (3) Y 03h 0 Y 04h date 05h 06h 10 years ...
Page 20
Figure 12. Counter update diagram SERIAL BUS 20/44 READ/WRITE BUFFER TRANSFER REGISTERS REGISTER REGISTER REGISTER SERIAL TRANSFER REGISTER REGISTER REGISTER REGISTER REGISTER 32KHz OSC DIVIDE BY 32768 1 Hz SECONDS COUNTER MINUTES COUNTER HOURS COUNTER DAY COUNTER ...
Page 21
Priority for IRQ/FT/OUT pin Three functions share pin 5 of the M41T00AUD. The oscillator fail interrupt (IRQ), the calibration frequency test output (FT) and the discrete logic output (OUT) all use this pin. In normal operation, when operating from ...
Page 22
Switchover thresholds While the M41T00AUD includes a precision reference for the backup switchover threshold not a fixed value, but depends on the backup voltage, V switchover at the lesser of the reference voltage (V This ensures that ...
Page 23
Trickle charge circuit The M41T00AUD includes a trickle charge circuit to be used with a backup capacitor illustrated in Table supply input. (The input nature is not depicted in the figure.) The trickle charge output function is ...
Page 24
Clock calibration The M41T00AUD oscillator is designed for use with a 12.5pF crystal load capacitance. With a nominal ±20 ppm crystal, the M41T00AUD will be accurate to ±35 ppm. When the calibration circuit is properly employed, accuracy improves to ...
Page 25
Example 2: Sign is 0 and (00010b). The 16-minute interval will be 513 + (60-3) * 512 + 512 = 491523 cycles long out of a possible 512 * 60 * ...
Page 26
Table 6. Digital calibration values Calibration value DC4-DC0 Decimal Binary 0 00000 1 00001 2 00010 3 00011 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 12 01100 13 01101 14 01110 ...
Page 27
Figure 15. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 – – –0.036 ppm/˚C 2 ± 0.006 ppm/˚C ...
Page 28
Audio section operation The audio section is comprised of five main parts. The input includes a summing amplifier. A minimum 10kΩ feedback resistor is required. With that and 20kΩ input resistors, the input signals will be summed at unity ...
Page 29
Figure 16. Audio section diagram 0.1μF 29/44 ...
Page 30
Table 7. MUTE and GAIN MUTE Binary 1 XXXX 0 1111 0 1110 0 1101 0 1100 0 1011 0 1010 0 1001 0 1000 0 0111 0 0110 0 0101 0 0100 0 0011 0 0010 0 0001 0 ...
Page 31
Gain The programmable gain stage follows the band pass filter. It provides between –33 and +12dB of gain, in 3dB steps (+/-1dB per step). The gain is selected by the GAIN bits, D3-D0 of register 08h, as listed in ...
Page 32
The other parameter pertains to the gain step size, a relative measurement shown in Table 16 as 3±1dB. For any gain setting in guaranteed to be between 2 and 4 dB higher (or lower). For example, even though ...
Page 33
Initial conditions The first time the M41T00AUD is powered up, some of its registers will automatically have their bits set to pre-determined levels as depicted in the set to benign levels to ensure predictable operation of the device. ST, ...
Page 34
Maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...
Page 35
DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under ...
Page 36
Table 12. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Active supply current CC1 I Standby supply current CC2 V Input Low voltage IL V Input High voltage IH Output Low voltage V ...
Page 37
Figure 18. Power down/up mode AC waveforms tPD SDA SCL Table 14. RTC power down/up AC characteristics Symbol Parameter t SCL and SDA at VIH before power down PD t SCL and SDA at VIH after ...
Page 38
Table 16. Audio section electrical characteristics, valid for 25°C (except where otherwise noted) AMB Symbol Parameter V Output offset voltage OO P Maximum output power O-MAX P Power supply rejection ratio SRR Gain step size Wake-up time ...
Page 39
Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner ...
Page 40
Figure 19. DFN16 (5mm x 4mm) package outline 1. Drawing is not to scale. 40/44 SIDE VIEW D D2 PIN BTM VIEW SEATING PLANE -C- b DFN16_ME ...
Page 41
Table 17. DFN16 (5mm x 4mm) package mechanical data mm Sym Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.20 b 0.20 0.25 D 5.00 E 4.00 D2 4.20 4.35 E2 2.30 2.45 e 0.50 L 0.30 0.40 K ...
Page 42
Part numbering Table 18. Ordering information scheme Example: Device type M41T00AUD Package D = Lead-free 5mm x 4mm DFN Temperature range 1 = 0°C to 70°C Shipping method ® ECOPACK lead-free ICs in tube ® ...
Page 43
Revision history Table 19. Document revision history Date Revision 01-May-2007 13-Dec-2007 1 Initial release. 2 Minor text changes; updated footnote 1 in Changes Table 13. 43/44 ...
Page 44
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...