M41T00AUDD1E STMICROELECTRONICS [STMicroelectronics], M41T00AUDD1E Datasheet - Page 18

• Manufacturer Part Number: M41T00AUDD1E
• Description: Serial real-time clock with audio
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

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Reading and writing the clock registers
The counters used to implement the timing chain in the real-time clock are not directly
accessed by the serial interface. Instead, as depicted in
buffered through a set of transfer registers. This ensures coherency of the timekeeping
function.
During writes of the timekeeping registers (00h to 06h), the write data is stored in the buffer
transfer registers until all the data is written, then the register contents are simultaneously
transferred to the counters thus updating them. The update is triggered either by a STOP
condition or by a write to one of the non RTC registers, 07h to 09h. If any of the buffer
transfer registers are not written, then the corresponding counters are not updated. Instead,
those counters will retain their previous contents when the update occurs.
Similar to the writes, reads access the buffer transfer registers. The device periodically
updates the registers with the counter contents. But during reads, the updates are
suspended. Timekeeping continues, but the registers are frozen until after a STOP
condition or a non RTC register (07h to 09h) is read. Suspending the updates ensures that
a clock roll-over does not occur during a user read cycle.
The seven clock registers may be read one byte at a time, or in a sequential block. The
calibration, audio and Control2 registers, location 07 h to 09 h, may be accessed
independently.
Provision has been made to ensure that a clock update does not occur while any of the
seven clock addresses are being read. During a clock register read (addresses 00h to 06h),
updates of the clock transfer buffer registers are halted. The clock counters continue to keep
time, but the contents of the transfer buffer registers is frozen at the time that the read
access began.
This prevents a transition of data during the READ. For example, without the halt function, if
the time incremented past midnight in the middle of an access sequence, the user might
begin reading at 11:59:59pm and finish at 12:00:00am. The data read might appear as
12:59:59 because the seconds and minutes were read before midnight while the hours were
read after. The device prevents this by halting the updates of the registers until after the
read access has occurred.
Figure
12, reads and writes are