74LVC245A-Q100 NXP [NXP Semiconductors], 74LVC245A-Q100 Datasheet

Page 1

... Octal bus transceiver; 3-state Rev. 1 — 3 September 2012 1. General description The 74LVC245A-Q100; 74LVCH245A-Q100 are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC245AD-Q100 74LVCH245AD-Q100 40 C to +125 C 74LVC245APW-Q100 74LVCH245APW-Q100 40 C to +125 C 74LVC245ABQ-Q100 74LVCH245ABQ-Q100 4. Functional diagram DIR ...

Page 3

... Fig 4. Description direction control data input/output ground (0 V) data input/output output enable input (active LOW) supply voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 September 2012 Octal bus transceiver; 3-state 74LVC245A-Q100 74LVCH245A-Q100 terminal 1 index area ...

Page 4

NXP Semiconductors 6. Functional description [1] Table 3. Function selection Inputs OE DIR [ HIGH voltage level LOW voltage level don’t care high impedance OFF-state. 7. ...

Page 5

NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table ...

Page 6

NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output current GND ...

Page 7

NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation nAn to nBn; nBn to nAn; see pd delay ...

Page 8

NXP Semiconductors 11. AC waveforms See Table 8 for measurement points V and V are typical output voltage levels that occur with the output load Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output ...

Page 9

NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance ...

Page 10

NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 11

NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 12

NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area ...

Page 13

NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history ...

Page 14

NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 15

NXP Semiconductors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any ...

Page 16

NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...